FSM question from HDLBits has different output than expected - verilog

Question

Question:-
Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.
The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).
(The original exam question asked for a state diagram only. But here, implement the FSM.)
My Code:
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
parameter a=0,b=1,c=2,d=3,e=4,f1=5,g1=6,h=7,i=8,per=9;
reg [3:0] state,ns;
always#(posedge clk) begin
if(~resetn)
ns<=a;
case(state)
a:ns<=resetn ? b : a;
b:ns<=c;
c:ns<=x ? d : c;
d:ns<=x ? d : e;
e:ns<=x ? f1 : d;
f1:ns<=y ? per : g1;
g1:ns<=y ? per : i;
per:ns<=resetn ? per : a;
i:ns<=resetn ? i : a;
endcase
end
assign state=ns;
assign f=(state==b);
assign g=(state==f1|state==g1|state==per);
endmodule

Answer 1

There is a problem with your reset logic. You should separate the reset clause from the rest of your logic; it should only be included in the if clause, and it should not be in the case statement.
Also, the case statement should be in an else clause:
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
parameter a=0,b=1,c=2,d=3,e=4,f1=5,g1=6,h=7,i=8,per=9;
reg [3:0] state;
always#(posedge clk) begin
if (~resetn) begin
state<=a;
end else begin
case(state)
a:state<=b;
b:state<=c;
c:state<=x ? d : c;
d:state<=x ? d : e;
e:state<=x ? f1 : d;
f1:state<=y ? per : g1;
g1:state<=y ? per : i;
endcase
end
end
assign f=(state==b);
assign g=(state==f1|state==g1|state==per);
endmodule
There is no need to have 2 state variables. I changed the FSM so that it only keeps state.