I have a component I would like to have 2 instantiations for, and I'd like to alternate sending/receiving data from each one every other clock cycle. Something like this:
component piece is
port(
clk : in std_logic;
a : in std_logic;
b : in std_logic;
c : in std_logic_vector(7 downto 0);
d : in std_logic_vector(7 downto 0)
);
end component;
piece_0 : if clk='0' generate
U_0: piece
port map(
clk => clk,
a => a,
b => b,
c => c,
d => d
);
end generate;
piece_1 : if clk='1' generate
U_1: piece
port map(
clk => clk,
a => a,
b => b,
c => c,
d => d
);
end generate;
When I compile I receive the warning Condition in IF GENERATE must be static.
When I synthesize it crashes...
Any ideas on how I can implement this?
Thanks!
A generate statement is evaluated during compilation, so the value of a signal has no relevance. It is used to instantiate blocks of code, either optionally (in the case of if ... generate), depending on some static value such as a constant or generic, or in a loop (in the case of for ... generate), for repeated instances of the same block of code.
You are trying to use it to control behavior at runtime, which is not valid. What you want instead is to instantiate both components and select the output with a mux. As your piece component has no outputs, it's a little difficult to provide some code that directly applies to your question, but in general:
U_0 : piece
port map (
clk => clk,
a => a,
...
q => q0
);
U_1 : piece
port map (
clk => clk,
a => a,
...
q => q1
);
q_muxed <= q0 when clk = '0' else q1;
I've written the mux using a simple concurrent statement, but there are other ways to do it. You may also want to consider using a signal other than clk as your select/switch. Using clk in a logical operation in most devices may have undesirable consequences, if it works at all.
Related
Question:-
Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.
The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).
(The original exam question asked for a state diagram only. But here, implement the FSM.)
My Code:
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
parameter a=0,b=1,c=2,d=3,e=4,f1=5,g1=6,h=7,i=8,per=9;
reg [3:0] state,ns;
always#(posedge clk) begin
if(~resetn)
ns<=a;
case(state)
a:ns<=resetn ? b : a;
b:ns<=c;
c:ns<=x ? d : c;
d:ns<=x ? d : e;
e:ns<=x ? f1 : d;
f1:ns<=y ? per : g1;
g1:ns<=y ? per : i;
per:ns<=resetn ? per : a;
i:ns<=resetn ? i : a;
endcase
end
assign state=ns;
assign f=(state==b);
assign g=(state==f1|state==g1|state==per);
endmodule
There is a problem with your reset logic. You should separate the reset clause from the rest of your logic; it should only be included in the if clause, and it should not be in the case statement.
Also, the case statement should be in an else clause:
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
parameter a=0,b=1,c=2,d=3,e=4,f1=5,g1=6,h=7,i=8,per=9;
reg [3:0] state;
always#(posedge clk) begin
if (~resetn) begin
state<=a;
end else begin
case(state)
a:state<=b;
b:state<=c;
c:state<=x ? d : c;
d:state<=x ? d : e;
e:state<=x ? f1 : d;
f1:state<=y ? per : g1;
g1:state<=y ? per : i;
endcase
end
end
assign f=(state==b);
assign g=(state==f1|state==g1|state==per);
endmodule
There is no need to have 2 state variables. I changed the FSM so that it only keeps state.
Hi I'm neophyte in Verilog and I have some question about designing module.
Is it okay to use top module's output as an input of submodule (Taking both module as sequentional logic)?
To my intuition about flip-flop, it seems to be okay but I'm not sure if this kind of approach is acceptable in verilog coding (anyway in logical or conventional). Should this kind of coding be avoided ?
module sample_top(
input a,
input b,
input c,
output d,
output e
);
//sequential
sample_submodule_1 SAMPLE_SUBMODULE_1(
//input of submodule
.A(a),
.B(b),
//output of submodule
.D(d)
);
//sequential
sample_submodule_2 SAMPLE_SUBMODULE_2(
//input of submodule
.C(c),
.D(d),
//output of submodule
.E(e)
);
Thanks for your answer.
The Verilog language does not really care about port directions. Hierarchy is just for creating namespaces and containers of behaviors. A port connection becomes a symbolic naming of a and A to a single wire object.
Other HDLs like VHDL do place restrictions on reading the values outputs. The difference between these HDLs is an artifact of how these languages resolve multiple drivers (which would take too much time to get into here). In Verilog you can see the effect of multiple driver resolution if one side of the port is a variable(reg), and the other side is a wire. Only the wire side of the port gets to see the resolved value of multiple drivers.
Output signals should not be referenced. It's recommendation (best practice). Many professional linters tread it as warning or notice.
Direct connection of output and submodule output is ok (your submodule 1).
Direct connection of output and submodule input is violation (your submodule 2).
Direct connection of output and function return is ok.
Direct connection of output and function input argument is violation.
Direct connection of output and task output argument is ok.
Direct connection of output and task input argument is violation.
Other references to output port are violation.
For example:
module SOME_MODULE(
clk,
rstn,
a,
b,
y
);
input clk;
input rstn;
input [3 : 0] a;
input [3 : 0] b;
output reg [5 : 0] y;
always #(posedge clk or negedge rstn) begin
if (~rstn)
y <= 5'd 0;
else
y <= y + a + b; // Reference to output port detected
end
endmodule
Should be described as:
module SOME_MODULE(
clk,
rstn,
a,
b,
y
);
input clk;
input rstn;
input [3 : 0] a;
input [3 : 0] b;
output [5 : 0] y;
reg [5 : 0] y_reg;
assign y = y_reg;
always #(posedge clk or negedge rstn) begin
if (~rstn)
y_reg <= 5'd 0;
else
y_reg <= y_reg + a + b;
end
endmodule
(Verilog) The following is a 32-bit Arithmetic Logic Unit (ALU) [see slides]. It has two 2-1 and one 3-1 MUX, a 32-bit Adder, a 32-bit subtractor, and a 16-bit multiplier. The function table shows different functions this ALU performs for different values of F (a 3-bit control signal). Notice the interconnect among different modules inside the ALU.
Please describe this ALU using Verilog. Your implementation should start with the smaller blocks showing in the ALU, and then using those smaller blocks to build the whole ALU. In other words, your implementation should promote reusability of smaller modules (i.e., modular). Optimize your implementation if possible.
function table in the image
module adding(r,a,b);
input[31:0] a;
input[31:0] b;
output[31:0] r;
assign r=a+b;
endmodule
module ALU(F,A,B,R);
input[2:0] F;
input[31:0] A;
input[31:0] B;
output[31:0] R;
reg R;
always #(F)
begin
if ( F == 3'b000 ) adding ad(R,A,B);
else if ( F == 3'b001 ) R = A+1;
else if ( F == 3'b010 ) R = A-B;
else if ( F == 3'b011 ) R = A-1;
else if ( F == 3'b10x ) R = A*B;
end
endmodule
this what I did so far but I got errors!! I will continue with the other statement as I know how to make the first small module
Notice some basic verilog syntax issues.
bit width mismatch in declaration of R.
sensitivity list not complete for the always block.
module instantiation is not allowed under a structural if.
I don't know if the undefined branches for F is intended, it is leading to behavior perhaps your don't want.
Since you are mainly working on module partition, it's related to the point 3. You will need to instantiate the basic (reusable) modules separately, and then select the outputs via F.
wire [31:0] adder_b;
wire [31:0] adder_result;
assign adder_b = F[0] ? 32'h1 : B; // select input outside 'adding'
adding ad (adder_result, A, ader_b);
always#(*)begin
if(F2:1] == 2'b00) R = adder_result;
...
end
There are many ways to write simple code in verilog.it depends on requirement some time here I presented different ways to write this code.
first by assign keyword and the second by case statements.
assign result = (opcode==3'b000) ? A+B :
((opcode==3'b001)? A+1 :
((opcode==3'b010)? A-B :
((opcode==3'b011)? A-1 : A*B)));
always #(*) begin
casex(opcode)
3'b000: result=A+B;
3'b001: result=A+1;
3'b010: result=A-B;
3'b011: result=A-1;
3'b1xx: result=A*B;
endcase
end
I am trying to wire a Verilog Structural description of an Edge-triggered T flip-flop with an synchronous reset (R). Here is the circuit for this element:
Now assume that I have already written the behavioral description for each block in this schematic , so here is my structural description for this circuit by instantiation of each of this blocks in the circuit:
module edge_trig_flipflop_structure (
input x,y,clk,
output q,
wire a,b,c,d
);
inv u1(c,q);
mux_2x1 u2 (q,c,x,a);
inv u3(d,y);
and_2_1 u4(b,a,d);
d_flipflop u5(b,clk,q);
endmodule
Is this a good efficient code for this circuit? In other words, do I really need the two extra wires used for the inverters which are the wires c and d Or, is there another efficient way to write this code?
Edit : Here is the code for each component to know the order of ports in the declaration of each component
module mux_2x1 (
input a,
input b,
input sel,
output reg c
);
always # (*) begin
case ( sel)
1'b0: c=a;
1'b1: c=b;
default : $dispaly ("error");
endcase
end
endmodule
module d_flipflop ( input d,clk , output reg q);
always # (posedge clk ) begin
q=d;
end
endmodule
module inv(output reg b, input a);
always # (a) begin
b=~a;
end
endmodule
module and_2_1 ( output reg c,input a,b);
always #(a or b) begin
if (a==1'b1 & b==1'b1)
c= 1'b1;
else
c=1'b0;
end
endmodule
By default, Verilog does not require you to declare all signals. If signals appear in port connections, they will implicitly be 1-bit wire types.
However, it is good practice to declare all signals explicitly with wire, as you have done.
You could also change the default behavior and require explicitly declared signals using this compiler directive:
`default_nettype none
Since you are also concerned about connections, it is a good practice to make connections by name instead of connections by position. It is more verbose, but it will help avoid simple connection errors. For example:
inv u1 (.b(c), .a(q));
I got compile errors on your module header. You probably meant to code it this way:
module edge_trig_flipflop_structure (
input x,y,clk,
output q
);
wire a,b,c,d;
For our school project I am trying to use linear feedback shift register for pseudo-random number generation on hardware (seven segment). I have written the LFSR and seven segment module, however I have trouble connecting the two modules with each other. The project synthesizes but the HDL Diagram does not show any connection between LFSR and seven segment module. Below is the code.
//main module
module expo(input clock, reset,
output a,b,c,d,e,f,g
);
wire [3:0]connect, clk, a,b,c,d,e,f,g;
LFSR_4_bit lfsr(
.clock(clock),
.LFSR(connect)
);
seven_seg seven(
.in(connect),
.reset(reset),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g)
);
endmodule
//LFSR module
module LFSR_4_bit(
input clock,
output reg[3:0]LFSR = 15
);
wire feedback = LFSR[4];
always #(posedge clock)
begin
LFSR[0] <= feedback;
LFSR[1] <= LFSR[0];
LFSR[2] <= LFSR[1];
LFSR[3] <= LFSR[2] ^ feedback;
LFSR[4] <= LFSR[3];
end
endmodule
//input and output for seven seg module
module sevenseg(
input reset,
input[3:0] in, //the 4 inputs for each display
output a, b, c, d, e, f, g, //the individual LED output for the seven segment along with the digital point
output [3:0] an // the 4 bit enable signal
);
Thanks for the help.
1) You instantiate seven_seg but the module is called module sevenseg This is a compile error.
2) Your LFSR has 4 bits 0 to 3, a fifth bit LFSR[4] is used, this is also a compile error.
Due to the compile errors I am not sure that your viewing the results of the current synthesis, as it should have failed. It is quite likely that you are viewing an old result before they were connected.
Other things I would change:
a) When you define wire [3:0]connect, clk, a,b,c,d,e,f,g; they are all 4 bits.
However as clock (not clk) and a,b,c,d,e,f,g are defined in your port list they are already declared. That line could just be wire [3:0]connect.
b) When initialising values for flip-flop and not using a reset it is better practise to use an initial begin : This is valid for FPGA's not for ASICs where you should use reset signals
initial begin
LFSR = 4'd15;
end