component VHDL code elabroation error - components

Question

I wrote a vhdl code for AES encryption and decryption and the encryption code has been worked but the decryption one gives me error when synthesize it
my code is
library ieee;
use ieee.std_logic_1164.all;
entity totdec is port
(
ipt : in std_logic_vector(1 TO 128); -- plain text
key : in std_logic_vector(1 TO 128); -- el key
plaint : out std_logic_vector(1 TO 128)
);
end totdec;
architecture behavior of totdec is
signal ibss : std_logic_vector(1 TO 128);
signal iptt : std_logic_vector(1 to 128);
signal k : std_logic_vector(1 to 128);
signal iop : std_logic_vector(1 to 128);
signal iop1 : std_logic_vector(1 to 128);
signal k0,k1,k2,k3,k4,k5,k6,k7,k8,k9,k10 : std_logic_vector(1 to 128);
signal ibss1,iop11,iop2,iop3,iop4,iop5,iop6,iop7,iop8,iop9 : std_logic_vector(1 to 128);
component keysched
port (
key : in std_logic_vector(1 to 128);
k0,k1,k2,k3,k4,k5,k6,k7,k8,k9,k10 : out std_logic_vector(1 to 128));
end component;
component fnround
port (
ipt : in std_logic_vector(1 TO 128);
k : in std_logic_vector(1 to 128);
ibss : out std_logic_vector(1 TO 128));
end component;
component iroundfunc
port
(
iptt : in std_logic_vector(1 to 128);
k : in std_logic_vector(1 to 128);
iop : out std_logic_vector(1 to 128));
end component;
component ikeyadd
port (
ipt : in std_logic_vector(1 TO 128);
k : in std_logic_vector(1 TO 128);
iop1 : out std_logic_vector(1 TO 128));
end component;
begin
keyschedx1 : keysched port map ( key=>key, k0=>k0, k1=>k1, k2=>k2, k3=>k3, k4=>k4, k5=>k5, k6=>k6, k7=>k7, k8=>k8, k9=>k9, k10=>k10 );
r_ound0 : fnround port map ( ipt=>ipt, k=>k10, ibss=>ibss1 );
r_ound1 : iroundfunc port map ( iptt=> ibss1, k=>k9, iop=> iop11 );
r_ound2 : iroundfunc port map ( iptt=> iop11, k=>k8, iop=> iop2 );
r_ound3 : iroundfunc port map ( iptt=> iop2, k=>k7, iop=> iop3 );
r_ound4 : iroundfunc port map ( iptt=> iop3, k=>k6, iop=> iop4 );
r_ound5 : iroundfunc port map ( iptt=> iop4, k=>k5, iop=> iop5 );
r_ound6 : iroundfunc port map ( iptt=> iop5, k=>k4, iop=> iop6 );
r_ound7 : iroundfunc port map ( iptt=> iop6, k=>k3, iop=> iop7 );
r_ound8 : iroundfunc port map ( iptt=> iop7, k=>k2, iop=> iop8 );
r_ound9 : iroundfunc port map ( iptt=> iop8, k=>k1, iop=> iop9 );
keyaddx1 : ikeyadd port map ( ipt=>iop9, k=>k0, iop1=>plaint );
end;
the error message is Elaboration failed for the instance : r_ound0