not a valid l-value - verilog compiler error - verilog

module fronter ( arc, length, clinic ) ;
input [7:0] arc;
output reg [7:0] length ;
input [1:0] clinic;
input en0, en1, en2, en3; // 11
// clock generator is here
g_cal A( en0) ;
g_cal B( en1) ;
g_cal C( en2) ;
g_cal D( en3) ;
always #( negedge arc, posedge clk )
case ( clinic )
2'b00 : { en3, en2, en1, en0 } = 4'b0001; // 23
2'b01 : { en3, en2, en1, en0 } = 4'b0010; // 24
2'b10 : { en3, en2, en1, en0 } = 4'b0100; // 25
2'b11 : { en3, en2, en1, en0 } = 4'b1000; // 26
default : { en3, en2, en1, en0 } = 4'bxxxx; // 27
endcase
// I am trying to change value of en to call corresponding intance with that
//corresponding en value
endmodule
module g_cal ( en ) ;
input en ;
// some other jobs, calling another instances after making some job
endmodule
when I compile, compiler gives me ;
verilog.v:23: error: en0 is not a valid l-value in Numerator.
verilog.v:11: : en0 is declared here as wire.
verilog.v:24: error: en1 is not a valid l-value in Numerator.
verilog.v:11: : en1 is declared here as wire.
verilog.v:25: error: en2 is not a valid l-value in Numerator.
verilog.v:11: : en2 is declared here as wire.
verilog.v:26: error: en3 is not a valid l-value in Numerator.
verilog.v:11: : en3 is declared here as wire.
verilog.v:27: error: en3 is not a valid l-value in Numerator.
verilog.v:11: : en3 is declared here as wire.
segmentation fault
How can I fix it ?
Why it gives error?
EDIT:
I have solved problem as ;
// I erased that line "input en0, en1, en2, en3; // 11"
// clock generator is here
g_cal A( 1'b0) ;
g_cal B( 1'b0) ;
g_cal C( 1'b0) ;
g_cal D( 1'b0) ;
always #( negedge arc, posedge clk )
/* erasing all those line
case ( clinic )
2'b00 : { en3, en2, en1, en0 } = 4'b0001; // 23
2'b01 : { en3, en2, en1, en0 } = 4'b0010; // 24
2'b10 : { en3, en2, en1, en0 } = 4'b0100; // 25
2'b11 : { en3, en2, en1, en0 } = 4'b1000; // 26
default : { en3, en2, en1, en0 } = 4'bxxxx; // 27
endcase
I will use if and else structure, and calling corresponding instance with 1'b1*/
// I am trying to change value of en to call corresponding intance with that
//corresponding en value
endmodule

You're trying assign to an input (which is bad). Change input en0, en1, en2, en3; to output reg en0, en1, en2, en3;. The reg is necessary since you are assigning to that variable within a procedural block (ie, an always or initial). The "not a valid l-value" message is trying to tell you this.
Also, I'm assuming that the 11, 23, 24, etc are stray line numbers from a copy-paste...

Problem has solved when I write ;
reg en0, en1, en2, en3 ;
initial begin
en0 <= 1'b0; en1 <= 1'b0;
en2 <= 1'b0; en3 <= 1'b0;
end
g_cal A( en0) ;
g_cal B( en1) ;
g_cal C( en2) ;
g_cal D( en3) ;
#Marty have emphasized important thing "The reg is necessary since you are assigning to that variable within a procedural block (ie, an always or initial)."

Related

MSP432 GPIO Output Voltage Too Low

I'm an undergraduate student. We have an assignment to use Energia and the MSP432-P401R microcontroller to create an OR gate and AND gate IC tester.
You place the IC in the tester circuit and the tester will first determine if the IC is an AND or OR IC. Then, it will indicate which gates on the chip are functioning properly.
My issue is regrading the logical HIGH output voltage of the MSP432. My input signals, a and b, are passed to the IC gates. When my "a" signal is logical HIGH, its voltage is 2.8V. When my "b" signal is logical HIGH, its voltage is 0.7V. This 0.7V is too low for my ICs to register as a HIGH input. I am reading the voltage directly from the MSP432 pin.
I have tried using different GPIO pins and resetting the board. However, the "b" signal is still 0.7V.
My code for setting up "a" and "b" are similar, so I'm not sure why they are outputting different voltages.
My code:
//IC TEST
//Gate inputs pin assignment
int APin=11;
int BPin=8; //other pins tried: 12, 18, 5
//Gate output read pins
int output1Pin=38;
int output2Pin=37;
int output3Pin=36;
int output4Pin=35;
//LED pins
int gate1LEDPin=31;
int gate2LEDPin=32;
int gate3LEDPin=33;
int gate4LEDPin=34; //Gate functioning indicators
int orLEDPin = 40;
int andLEDPin= 39; //Logic of IC indicators
//Truth Table Arrays with inputs a and b
int aValue[]={0, 0, 1, 1};
int bValue[]={0, 1, 0, 1};
int orTrue[]={0, 1, 1, 1};
int andTrue[]={0, 0, 0, 1};
//Function Declaration
int workTest(int,int); //checks if gate is working
//by comparing gate output to
//expected truth result
int logicTest(); //Returns 0 for OR IC, 1 for AND IC
//Progrram variables
int i; //for loop counter
int gate1Result;
int gate2Result;
int gate3Result;
int gate4Result; //Stores number of times gate outputs
//correct value for each ab input
int logicRead; //0 is OR gate. 1 is AND gate
//--------------SETUP-----------------
void setup()
{
Serial.begin(9600);
pinMode(APin, OUTPUT);
pinMode(BPin, OUTPUT);
pinMode(output1Pin, INPUT);
pinMode(output2Pin, INPUT);
pinMode(output3Pin, INPUT);
pinMode(output4Pin, INPUT); //gate output reads
pinMode(orLEDPin, OUTPUT);
pinMode(andLEDPin, OUTPUT);
pinMode(gate1LEDPin, OUTPUT);
pinMode(gate2LEDPin, OUTPUT);
pinMode(gate3LEDPin, OUTPUT);
pinMode(gate4LEDPin, OUTPUT);
}
//END SETUP
//-----------------LOOP---------------------
void loop()
{
gate1Result = 0;
gate2Result = 0;
gate3Result = 0;
gate4Result = 0;
//test IC for its logic function
logicRead = logicTest(); //logicTest returns 0 for OR, 1 for AND
if(logicRead == 9) //logic of IC cannot be determined
{
Serial.println("Try again");
}
if(logicRead != 9)
{
for(i=0; i<4; i++)
{
digitalWrite(APin, aValue[i]); //Load ith value of aValue array
digitalWrite(BPin, bValue[i]); //Load ith value of bValue array
Serial.print("AB = ");
Serial.print(aValue[i]);
Serial.println(bValue[i]);
delay(4000); //Stabilize input signals
if(logicRead == 0) //OR Testing
{
Serial.print("OR Output should be ");
Serial.println(orTrue[i]);
Serial.print("Gate 1: ");
gate1Result = gate1Result + workTest(orTrue[i], output1Pin);
Serial.print("Gate 2: ");
gate2Result = gate2Result + workTest(orTrue[i], output2Pin);
Serial.print("Gate 3: ");
gate3Result = gate3Result + workTest(orTrue[i], output3Pin);
Serial.print("Gate 4: ");
gate4Result = gate4Result + workTest(orTrue[i], output4Pin);
}
if(logicRead == 1) //AND Testing
{
Serial.print("AND Output should be ");
Serial.println(andTrue[i]);
Serial.print("Gate 1: ");
gate1Result = gate1Result + workTest(andTrue[i], output1Pin);
Serial.print("Gate 2: ");
gate2Result = gate2Result + workTest(andTrue[i], output2Pin);
Serial.print("Gate 3: ");
gate3Result = gate3Result + workTest(andTrue[i], output3Pin);
Serial.print("Gate 4: ");
gate4Result = gate4Result + workTest(andTrue[i], output4Pin);
}
}
//Write gate 1 LED
if(gate1Result == 4)
{
digitalWrite(gate1LEDPin, HIGH);
Serial.println("Gate 1 works");
}
else
{
digitalWrite(gate1LEDPin, LOW);
Serial.println("Gate 1 FAIL");
}
//Write gate 2 LED
if(gate2Result == 4)
{
digitalWrite(gate2LEDPin, HIGH);
Serial.println("Gate 2 works");
}
else
{
digitalWrite(gate2LEDPin, LOW);
Serial.println("Gate 2 FAIL");
}
//Write gate 3 LED
if(gate3Result == 4)
{
digitalWrite(gate3LEDPin, HIGH);
Serial.println("Gate 3 works");
}
else
{
digitalWrite(gate3LEDPin, LOW);
Serial.println("Gate 3 FAIL");
}
//Write gate 4 LED
if(gate4Result == 4)
{
digitalWrite(gate4LEDPin, HIGH);
Serial.println("Gate 4 works");
}
else
{
digitalWrite(gate4LEDPin, LOW);
Serial.println("Gate 4 FAIL");
}
}
Serial.println();
Serial.println();
delay(10000); //Wait 10 sec before running code again
}//End void loop
//-----------Function Definitions-----------------------
//This function tests if all gates of the IC are working
//Returns 1 if gate is functioning
//Returns 0 if gate is not functioning
int workTest(int truth, int gateNum)
{
int gateRead = 0; //Updates for each gate output
int result = 0; //TotResult is 1 for all gates pass, 0 for any gate fail
gateRead= digitalRead(gateNum);
if(gateRead == truth)
{
result = 1;
}
else
{
result = 0;
}
Serial.println(gateRead);
return result; //1 for pass, 0 for gate fails
}
//This function tests the logic of the IC
//Returns 1 if IC is an AND gate
//Returns 0 if IC is an OR gate
//Allows for 1 broken gate
//If more than 1 gate broken, logic cannot
//be determined
int logicTest()
{
int aVal[]={0, 1};
int bVal[]={1, 0};
int outputCount = 0;
int logicGate = 0;
int c;
int gate1;
int gate2;
int gate3;
int gate4;
for(c=0; c<2; c++) //only testing ab = 01 and ab = 10
{
digitalWrite(APin, aVal[c]);
digitalWrite(BPin, bVal[c]);
delay(1000); //Stabilize input delay
gate1=digitalRead(output1Pin);
gate2=digitalRead(output2Pin);
gate3=digitalRead(output3Pin);
gate4=digitalRead(output4Pin);
outputCount = outputCount + gate1 + gate2 + gate3 + gate4;
}
if(outputCount < 3) //IC is likely AND gate w/ 1 broken gate
{
logicGate = 1;
Serial.println("IC is an AND gate");
digitalWrite(andLEDPin, HIGH);
digitalWrite(orLEDPin, LOW);
}
else if(outputCount > 5 && outputCount < 9) //IC is likely OR gate w/ 1 broken gate
{
logicGate = 0;
Serial.println("IC is an OR gate");
digitalWrite(andLEDPin, LOW);
digitalWrite(orLEDPin, HIGH);
}
else
{
logicGate = 9;
digitalWrite(andLEDPin, LOW);
digitalWrite(orLEDPin, LOW);
Serial.println("Logic of IC could not be determined");
Serial.println("IC could be broken. Make sure IC is connected properly.");
Serial.println();
}
return logicGate;
}
Here is the circuit setup:

How to solve "Unresolved defparam reference" Error in ModelSIM?

I've generated a reciprocal ROM using Quartus II and I've developed a circuit that calculates the hyperbolic tangent. I'm facing the following error when I try to simulate a testbench of my circuit. Note that I've used the ROM as an instantiate in my circuit.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.address_aclr_a.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.clock_enable_input_a.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.clock_enable_output_a.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.init_file.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.intended_device_family.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.lpm_hint.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.lpm_type.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.numwords_a.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.operation_mode.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.outdata_aclr_a.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.outdata_reg_a.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.widthad_a.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.width_a.
Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.width_byteena_a.
and this is the Verilog output of the ROM that I've generated in Quartus II:
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RecipROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RecipROM (
address,
clock,
q);
input [2:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../initROM.mif",
altsyncram_component.intended_device_family = "Cyclone IV GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 3,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../initROM.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../initROM.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: #address_a 0 0 3 0 address 0 0 3 0
// Retrieval info: CONNECT: #clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 #q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RecipROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RecipROM.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RecipROM.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RecipROM.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RecipROM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RecipROM_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RecipROM_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
How can I solve this error?
Probably you just need to load the Altera libraries in Modelsim:
using GUI: Simulate > Start Simulation > Libraries > Add > altera_mf_ver
using console: add -L altera_mf_ver to your command.

ModelSim unexpected z input

I'm building a simple 7-segment display.
I didn't have errors when I was compiling the module and testbench.
But, when I'm simulating, I keep getting z value as input. Why do I get the z?
Verilog code as below :
module dec_7seg(d, seg);
input [3:0]d;
output [7:0]seg;
assign seg[1]= (d[1]&~d[2]) | d[0] | (~d[1]&d[2]) | (d[2]&~d[3]);
assign seg[2]= (~d[0]&d[1]) | (~d[1]&~d[2]&~d[3]) | (d[1]&d[2]) | (d[0]&~d[1]&d[3]);
assign seg[3]= (~d[1]&~d[3]) | (d[0]&d[1]) | (d[2]&~d[3]) | (d[0]&d[2]);
assign seg[4]= (~d[1]&~d[3]) | (d[1]&~d[2]&d[3]) | (~d[1]&d[2]) | (d[2]&~d[3]) | (d[0]&~d[3]);
assign seg[5]= (~d[2]&d[3]) | (~d[0]&d[1]) | (~d[0]&~d[2]) | (d[0]&~d[1]) | (~d[0]&d[3]);
assign seg[6]= (~d[1]&~d[2]) | (~d[0]&~d[2]&~d[3]) | (~d[0]&~d[1]) | (~d[0]&d[2]&d[3]) | (d[0]&~d[2]&d[3]) | (d[0]&d[2]&~d[3]);
assign seg[7]= (~d[1]&~d[3]) | (~d[0]&d[2]) | (d[1]&d[2]) | (~d[0]&d[1]&d[3]) | (d[0]&~d[1]&~d[2]);
endmodule
Testbench :
`timescale 1ns/1ps
module tb_dec_7seg_selfchecking();
reg [3:0] d;
wire [7:0] seg;
dec_7seg U0(.d(d),.seg(seg));
initial begin
d=4'b0000; #10; //0000
if(seg !== 8'b11111100)$display("0 fail");
d=4'b1000; #10; //0001
if(seg !== 8'b01100000)$display("1 fail");
d=4'b0100; #10; //0010
if(seg !== 8'b11011010)$display("2 fail");
d=4'b1100; #10; //0011
if(seg !== 8'b11110010)$display("3 fail");
d=4'b0010; #10; //0100
if(seg !== 8'b01100110)$display("4 fail");
d=4'b1010; #10; //0101
if(seg !== 8'b10110110)$display("5 fail");
d=4'b0110; #10; //0110
if(seg !== 8'b10111110)$display("6 fail");
d=4'b1110; #10; //0111
if(seg !== 8'b11100100)$display("7 fail");
d=4'b0001; #10; //1000
if(seg !== 8'b11111110)$display("8 fail");
d=4'b1001; #10; //1001
if(seg !== 8'b11100110)$display("9 fail");
d=4'b0101; #10; //1010
if(seg !== 8'b11111010)$display("a fail");
d=4'b1101; #10; //1011
if(seg !== 8'b00111110)$display("b fail");
d=4'b0011; #10; //1100
if(seg !== 8'b00011010)$display("c fail");
d=4'b1011; #10; //1101
if(seg !== 8'b01111010)$display("d fail");
d=4'b0111; #10; //1110
if(seg !== 8'b11011110)$display("e fail");
d=4'b1111; #10; //1111
if(seg !== 8'b10001110)$display("f fail");
end
endmodule
You do not drive seg[0]. An output port is implicitly declared as type wire, and wire types default to z when undriven. To get rid of the z, since your testbench expects bit 0 to be 0, you could add this line inside your dec_7seg module:
assign seg[0]= 0;

How to use TSL2301 and make clock delay in usart

I am working on a line scan ccd sensor named TSL2301 .I want to read pixels by USART of stm32f103 but always i just could receive 0xFF , did anybody work with this sensor to help me?
I used Usart synchronous mode of STM32f10x , I sent some order to sensor by Usart and want to make 8 clock delay after each order . how can i do it?
int count=0;
int i=0;
uint8_t data[102]={0};
USART_ClockInitStructure.USART_Clock = USART_Clock_Enable;
USART_ClockInitStructure.USART_CPOL = USART_CPOL_High;
USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
USART_ClockInitStructure.USART_LastBit = USART_LastBit_Enable;
USART_ClockInit(USARTy, &USART_ClockInitStructure);
USART_InitStructure.USART_BaudRate = 2200000;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No ;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USARTy, &USART_InitStructure);
/* Configure the USARTy */
USART_Init(USARTy, &USART_InitStructure);
/* Enable the USARTy */
USART_Cmd(USARTy, ENABLE);
while(1)
{
while(count < 3)
{
USART_SendData(USARTy,0xFF);
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
count++;
}
count=0;
USART_SendData(USARTy,0x1b); //RESET command
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
USART_SendData(USARTy,0x1b);
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
USART_SendData(USARTy,0x1b);
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
USART_SendData(USARTy,0x08); //StartInt Command
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
while(count < 20 )//DelayIntegrationTime() ;
{
USART_SendData(USARTy,0xFF);
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
count++;
}
count = 0;
USART_SendData(USARTy,0x10); //SampleInt Command
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
USART_SendData(USARTy,0x02); //ReadPixel Command
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
while(count < 2)
{
USART_SendData(USARTy,0xFF);
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
count++;
}
count = 0;
USART_Cmd(USARTy, DISABLE);
USART_ClockInitStructure.USART_CPOL = USART_CPOL_High;
USART_ClockInitStructure.USART_CPHA = USART_CPHA_1Edge;
USART_ClockInit(USARTy, &USART_ClockInitStructure);
USART_Init(USARTy, &USART_InitStructure);
USART_Cmd(USARTy, ENABLE);
/*read pixels*/
for (i = 0; i < 102; i++)
{
while(USART_GetFlagStatus(USARTy, USART_FLAG_RXNE) == RESET);
data[i] = USART_ReceiveData(USARTy);
while(count < 1)
{
USART_SendData(USARTy,0xFF);
while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET);
count++;
}
count = 0;
}
USART_Cmd(USARTy, DISABLE);
USART_ClockInitStructure.USART_CPOL = USART_CPOL_High;
USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
USART_ClockInit(USARTy, &USART_ClockInitStructure);
USART_Init(USARTy, &USART_InitStructure);
USART_Cmd(USARTy, ENABLE);
}
There is different USART timing diagrams in STM32F103 reference manual and TAOS datasheet.
I think they will not work together in USART mode.
As an Idea, you can try to use UART instead of USART. And clock the device using MCO or other clock source. I think it should work.
It this case all delays you can do with timer.
PS: But there is one more problem you should solve, is to synchronize output of UART with clock source. I need to read stm32 manual more carefuly to tell you how to do it. I'll do it later

component VHDL code elabroation error

I wrote a vhdl code for AES encryption and decryption and the encryption code has been worked but the decryption one gives me error when synthesize it
my code is
library ieee;
use ieee.std_logic_1164.all;
entity totdec is port
(
ipt : in std_logic_vector(1 TO 128); -- plain text
key : in std_logic_vector(1 TO 128); -- el key
plaint : out std_logic_vector(1 TO 128)
);
end totdec;
architecture behavior of totdec is
signal ibss : std_logic_vector(1 TO 128);
signal iptt : std_logic_vector(1 to 128);
signal k : std_logic_vector(1 to 128);
signal iop : std_logic_vector(1 to 128);
signal iop1 : std_logic_vector(1 to 128);
signal k0,k1,k2,k3,k4,k5,k6,k7,k8,k9,k10 : std_logic_vector(1 to 128);
signal ibss1,iop11,iop2,iop3,iop4,iop5,iop6,iop7,iop8,iop9 : std_logic_vector(1 to 128);
component keysched
port (
key : in std_logic_vector(1 to 128);
k0,k1,k2,k3,k4,k5,k6,k7,k8,k9,k10 : out std_logic_vector(1 to 128));
end component;
component fnround
port (
ipt : in std_logic_vector(1 TO 128);
k : in std_logic_vector(1 to 128);
ibss : out std_logic_vector(1 TO 128));
end component;
component iroundfunc
port
(
iptt : in std_logic_vector(1 to 128);
k : in std_logic_vector(1 to 128);
iop : out std_logic_vector(1 to 128));
end component;
component ikeyadd
port (
ipt : in std_logic_vector(1 TO 128);
k : in std_logic_vector(1 TO 128);
iop1 : out std_logic_vector(1 TO 128));
end component;
begin
keyschedx1 : keysched port map ( key=>key, k0=>k0, k1=>k1, k2=>k2, k3=>k3, k4=>k4, k5=>k5, k6=>k6, k7=>k7, k8=>k8, k9=>k9, k10=>k10 );
r_ound0 : fnround port map ( ipt=>ipt, k=>k10, ibss=>ibss1 );
r_ound1 : iroundfunc port map ( iptt=> ibss1, k=>k9, iop=> iop11 );
r_ound2 : iroundfunc port map ( iptt=> iop11, k=>k8, iop=> iop2 );
r_ound3 : iroundfunc port map ( iptt=> iop2, k=>k7, iop=> iop3 );
r_ound4 : iroundfunc port map ( iptt=> iop3, k=>k6, iop=> iop4 );
r_ound5 : iroundfunc port map ( iptt=> iop4, k=>k5, iop=> iop5 );
r_ound6 : iroundfunc port map ( iptt=> iop5, k=>k4, iop=> iop6 );
r_ound7 : iroundfunc port map ( iptt=> iop6, k=>k3, iop=> iop7 );
r_ound8 : iroundfunc port map ( iptt=> iop7, k=>k2, iop=> iop8 );
r_ound9 : iroundfunc port map ( iptt=> iop8, k=>k1, iop=> iop9 );
keyaddx1 : ikeyadd port map ( ipt=>iop9, k=>k0, iop1=>plaint );
end;
the error message is Elaboration failed for the instance : r_ound0

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