12-hour clock code output "pm" has one hour less than the standard answer - verilog

Question

HDLBits 12-hour clock
I wrote the answer for this question, but something wrong occurred. I can't find out where I'm wrong because the answer just tells me how many mismatches I have. Can some one tell me please?
Here are results from HDLBIts:
result
result
result
And here is my code:
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
wire [1:0] ssc, mmc, hhc;
assign ssc[0] = ss[3]&ss[0];
counter4buenld cssl(clk, ena, reset, ssc[0], 4'h0, ss[3:0]);
assign ssc[1] = ss[4]&ss[6]&ssc[0];
counter4buenld cssh(clk, ena&ssc[0], reset, ssc[1], 4'h0, ss[7:4]);
assign mmc[0] = mm[3]&mm[0]&ssc[1];
counter4buenld cmml(clk, ena&ssc[1], reset, mmc[0], 4'h0, mm[3:0]);
assign mmc[1] = mm[4]&mm[6]&mmc[0];
counter4buenld cmmh(clk, ena&mmc[0], reset, mmc[1], 4'h0, mm[7:4]);
assign hhc[0] = hh[3]&hh[0]&mmc[1];
assign hhc[1] = hh[4]&hh[1]&mmc[1];
counter4buenld chhl(clk, ena&mmc[1], 1'b0, reset|hhc[0]|hhc[1], {2'b00, reset, ~reset}, hh[3:0]);
counter4buenld chhh(clk, ena&hhc[0], 1'b0, reset|hhc[1], {3'b000, reset}, hh[7:4]);
reg pml;
assign pm = pml;
always#(posedge clk) begin
if(reset) begin
pml <= 1'b0;
end
else begin
if(hh[4]&hh[0]&mmc[1]) begin
pml <= ~pml;
end
else begin
pml <= pml;
end
end
end
endmodule
module counter4buenld(
input clk,
input ena,
input reset,
input load,
input [3:0] d,
output reg [3:0] q
);
always#(posedge clk) begin
if(reset)
q <= 4'h0;
else
if(load)
q <= d;
else
q <= q + ena;
end
endmodule

Answer 1

The HDLBits waveform snapshots do not give you enough visibility to debug your problem. You need to create your own testbench and view the complete waveforms.
When you do so, you would see that your hour increments from 9 to 11. It skips 10.
Your Verilog code is too difficult to understand. Here is a simpler approach, including a trivial testbench:
module top_module (
input clk,
input reset,
input ena,
output reg pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
reg [7:0] hhd, mmd, ssd;
function [7:0] bcd ([7:0] in);
bcd[3:0] = in % 10;
bcd[7:4] = in / 10;
endfunction
assign ss = bcd(ssd);
assign mm = bcd(mmd);
assign hh = bcd(hhd);
always#(posedge clk) begin
if (reset) begin
pm <= 0;
end else if (ena && hhd==11 && mmd==59 && ssd==59) begin
pm <= ~pm;
end
end
always#(posedge clk) begin
if (reset) begin
ssd <= 0;
end else if (ena) begin
if (ssd==59) begin
ssd <= 0;
end else begin
ssd <= ssd + 1;
end
end
end
always#(posedge clk) begin
if (reset) begin
mmd <= 0;
end else if (ena && ssd==59) begin
if (mmd==59) begin
mmd <= 0;
end else begin
mmd <= mmd + 1;
end
end
end
always#(posedge clk) begin
if (reset) begin
hhd <= 12;
end else if (ena && mmd==59 && ssd==59) begin
if (hhd==12) begin
hhd <= 1;
end else begin
hhd <= hhd + 1;
end
end
end
endmodule
module tb;
bit clk;
bit ena=1;
bit reset=1;
wire pm;
wire [7:0] hh;
wire [7:0] mm;
wire [7:0] ss;
top_module dut (
// Inputs:
.clk (clk),
.ena (ena),
.reset (reset),
// Outputs:
.hh (hh),
.mm (mm),
.pm (pm),
.ss (ss)
);
always #5 clk++;
initial begin
#12 reset=0;
#5ms $finish;
end
endmodule
Compare MINE vs. YOURS: