I'm using curl in my code and running through Makefile. but while running with "make" command its giving error like "curl/curl.h: No such file or directory".
Here below is my makefile content.
CXX = /home/directory/Documents/xyz/l4t-gcc/bin/aarch64-buildroot-linux-gnu-cc
path = /home/directory/Documents/xyz/l4t-gcc/bin/
CFLAGS = -Wall
#INCLUDE = -I/usr/local/include -I/usr/include -Iinclude
#LDFLAGS = -L/usr/local/lib -I/usr/lib
LDLIBS = -lcurl
SOURCES = src/sms_wrapper.c src/twilio.c
OUT = bin/sms_wrapper
all: build
build: $(SOURCES)
$(CXX) -o $(OUT) $(CFLAGS) $(SOURCES) $(LDLIBS)
clean:
rm -rf bin/sms_wrapper
I install curl and added all things in Makefile which is needed for curl library.
Does anyone have any suggestions or idea for resolving this thing !
Related
I followed this guide to build a cross compiler for Raspberry Pi ARMv7. It works fine (compiles ok hello world) but the problem is I can't use Raspberry Pi libraries such as wiringpi, sqlite etc.
This is my Makefile.
CC = /opt/cross-pi-gcc/bin/arm-linux-gnueabihf-g++
QUOTE := "
CFLAGS = -g -lwiringPi -pthread -lpthread
PROGRAM = lora
OBJDIR = obj
CPP_SRCS += \
src/main.cpp \
src/radio/sx1276/sx1276.cpp \
src/radio/radio.cpp \
OBJ_FILES += \
$(OBJDIR)/main.o \
$(OBJDIR)/sx1276.o \
$(OBJDIR)/radio.o \
all: make_dir $(OBJ_FILES)
$(CC) $(OBJ_FILES) $(CFLAGS) -o $(PROGRAM)
make_dir:
mkdir -p $(OBJDIR)
$(OBJDIR)/main.o: src/main.cpp
$(CC) $(CFLAGS) -c -o $# $<
$(OBJDIR)/service.o: src/service/service.cpp
$(CC) $(CFLAGS) -c -o $# $<
$(OBJDIR)/sx1276.o: src/radio/sx1276/sx1276.cpp
$(CC) $(CFLAGS) -c -o $# $<
$(OBJDIR)/radio.o: src/radio/radio.cpp
$(CC) $(CFLAGS) -c -o $# $<
clean:
rm $(PROGRAM)
rm -rf $(OBJDIR)
The error I'm getting:
/opt/cross-pi-gcc/lib/gcc/arm-linux-gnueabihf/8.3.0/../../../../arm-linux-gnueabihf/bin/ld: cannot find -lwiringPi
I copied some libraries from my Pi into a folder on my home dir with this command.
rsync -vR --progress -rl --delete-after --safe-links pi#192.168.1.PI:/{lib,usr,opt/vc/lib} $HOME/raspberrypi/rootfs
Which I found it here.
But I'm not sure how to link them. Did I overlook something?
Note: The piece of code I'm trying to compile was compiling fine on Windows's cross-compiler.
I'm trying to setup a tool-chain on my Linux desktop. I'm using Manjaro.
You have to tell the linker where to look for the libraries.
You can add the flag -L$HOME/raspberrypi/rootfs/usr/lib, or wherever libwiringPi.so is located.
You have to point the compiler to the right headers as well. For that you use the -I flag. E.g. -I$HOME/raspberrypi/rootfs/usr/include. This goes in the CFLAGS of the targets that include wiringPi.h.
Also, -lwiringPi -pthread -lpthread don't belong in the CFLAGS, they are linker flags. You only need them in the target that builds PROGRAM. You could add a separate variable LDFLAGS, for example.
I'm trying to compile a project that has multiple *.c files and *.h file when I type the following command:
$gcc -c -I ../hdr main.c gestic.c menu.c
the hdr folder is where the *.h files are located, the .o files are created but when I try to link them using the command:
$gcc -o main.o gestic.o menu.o
I see errors
gestic.c:(.text+0x..): undefined reference to functions that are declared in *.h files
$gcc -Wall -c -I../hdr -o main.o main.c
$gcc -Wall -c -I../hdr -o menu.o menu.c
$gcc -Wall -c -I../hdr -o gestic.o gestic.c
$gcc -Wall -o myprogram main.o menu.o gestic.o
Using a Makefile is very common for this task
example (untested) Makefile:
CC=gcc
CFLAGS=-Wall -I../hdr
all: myprogram
myprogram: main.o menu.o gestic.o
$(CC) -o $# $^
gestic.o: gestic.c
$(CC) $(CFLAGS) -c -o $# $<
main.o: main.c
$(CC) $(CFLAGS) -c -o $# $<
menu.o: menu.c
$(CC) $(CFLAGS) -c -o $# $<
Try:
$ gcc main.o gestic.o menu.o
-o filename: Place output in filename
Firstly header files are not included, secondly you might use the function that doesn't contain the definition.
The message undefined reference to 'function_name' implies that of all the object files you're giving to the linker, none of them has a definition for function_name. That means that either
You're not linking with *.o
*.c (as compiled) does not contain a definition for function_name -- by 'as compiled' I mean with all of the various preprocessor options you use on it.
here -Iinclude/
try,
gcc -c file.c -I<include_dir>
If you compile more files better to have makefile to create the objects of those files, link those objects along with header.
Sample makefile,
CC = gcc
CFLAGS = -Wall
INCLUDE = sample.h
OBJ = samople1.o sample2.o
%.o: %.c $(INCLUDE)
$(CC) $(CFLAGS) -c -o $# $<
go: $(OBJ)
gcc $(CFLAGS) -o $# $^
I came across a very strange issue of makefile, here it is:
System: Linux CentOS 6
In the beginning, the name of makefile is “makefile”, its sample contents:
OPTFLAGS = -Wall -g -O
CXX = g++
INC = -I/usr/local/include -I/usr/include
LIBS = -L/usr/local/lib -L/usr/lib64
CXXFLAGS = $(OPTFLAGS) $(INC)
SOURCES = file1.cpp file2.cpp file3.cpp
OBJECTS = $(SOURCES:.cpp=.o)
EXECUTABLE = mybin
$(EXECUTABLE): $(OBJECTS)
$(CXX) $(CXXFLAGS) $(INC) $(LIBS) $(OBJECTS) -o $#
file1.o : file1.cpp
file2.o : file2.cpp
file3.o : file3.cpp
.PHONY: clean
clean:
rm -f $(EXECUTABLE) *.o core*
I got following err after I ran “make”:
g++: file3.o: No such file or directory
I have a workaround to add a dummy file after file3:
dummy.o : dummy.cpp
This way I could build successfully.
And I know that I can delete all these lines:
file1.o : file1.cpp
file2.o : file2.cpp
file3.o : file3.cpp
let make to build using default settings, I could build successfully this way.
I also tried to just rename “makefile” to “Makefile”, and with following lines without dummy line:
file1.o : file1.cpp
file2.o : file2.cpp
file3.o : file3.cpp
To my surprise, I could build successfully this way.
Could anyone explain why I got error of “No such file or directory” for the last file3 in the beginning?
Following is the error output:
g++ -g -Wall -O -I/usr/local/include -I/usr/include -c -o file1.o file1.cpp
g++ -g -Wall -O -I/usr/local/include -I/usr/include -c -o file2.o file2.cpp
g++ -g -Wall -O -I/usr/local/include -I/usr/include -I/usr/local/include -I/usr/include -L/usr/local/lib -L/usr/lib64 -lsybdb file1.o file2.o file3.o -o mybin
g++: file3.o: No such file or directory
make: *** [mybin] Error 1
Following is the output after I added dummy line:
g++ -Wall -g -O -I/usr/local/include -I/usr/include -c -o file1.o file1.cpp
g++ -Wall -g -O -I/usr/local/include -I/usr/include -c -o file2.o file2.cpp
g++ -Wall -g -O -I/usr/local/include -I/usr/include -c -o file3.o file3.cpp
g++ -Wall -g -O -I/usr/local/include -I/usr/include -I/usr/local/include -I/usr/include -L/usr/local/lib -L/usr/lib64 -lsybdb file1.o file2.o file3.o -o mybin
I tried to rename "makefile" to "Makefile" again, and it doesn't work this time.
Ufffff!! Found your problem.
When you wrote
file1.o : file1.cpp
file2.o : file2.cpp
file3.o : file3.cpp
in your makefile a deamon came and introduced a TAB after the line file3.o : file3.cpp so make instead of taking implicit rule thought you are specifying explicit rule. For file1.o and file2.o it used implicit rule but for file3.o it assumed your are specifying explicit rule because of that TAB, but you had given it a blank TAB so file3.o was never built.
Now when you added dummy.o:dummy.cpp the TAB moved below that line so file3.o was compiled. When you were experimenting around you deleted that TAB that's why renaming makefile to Makefile seemed to work.
Just FYI: there is no difference between Makefile or makefile both are treated equally by make, except when both Makefile and makefile files are there in same folder and you give make then makefile is executed instead of Makefile
I was doing makefile test for creating static library and creating dynamic library from it. I have foo.h foo.c bar.c and main.c files in my directory.
I wrote a Makefile as follows:
#This makefile demonstrate the shared and static library creation.
CFLAGS = -Wall -Werror -fPIC
CFLAGS1 = -Wall
inc = /home/betatest/Public/implicit-rule-archive
all : foo.o bar.o libfoo.a libfoo.so run
foo.o: foo.c foo.h
#echo "Making the foo.o"
$(CC) -c $(CFLAGS) $< -o $#
bar.o : bar.c foo.h
#echo "Making the bar.o"
$(CC) -c $(CFLAGS) $< -o $#
libfoo.a(foo.o bar.o) : foo.o bar.o
ar cr $# $^
libfoo.so : libfoo.a
$(CC) -shared -o $# $^
run : main.c
$(CC) -L$(inc) $(CFLAGS1) -o $# $< -lfoo
.PHONY : clean
clean :
-rm -f *.o run libfoo.*
while making it gives the following the following errors:
Making the foo.o
cc -c -Wall -Werror -fPIC foo.c -o foo.o
Making the bar.o
cc -c -Wall -Werror -fPIC bar.c -o bar.o
make: *** No rule to make target 'libfoo.a', needed by 'all'. Stop.
I have written the archive statement as :
libfoo.a(foo.o bar.o) : foo.o bar.o
ar cr $# $^
from this to:
libfoo.a(*.o) : *.o
ar cr $# $^
Can I write the statement like this because in both the cases the error is the same.
I don't understand where I am going wrong. Thanks!!!!!
Instead of libfoo.a(foo.o bar.o) you want plain libfoo.a : foo.o bar.o.
Another thing is that .a files are normally built for linking against the final executable, hence object files for .a are compiled as position-dependent code. Shared libraries, on the other hand, require code compiled as position independent.
Hence, you can:
Get rid of libfoo.a.
Produce header dependencies automatically.
Establish complete dependencies on your targets so that make -j works robustly.
Set rpath so that run always finds libfoo.so in its directory.
This way:
CFLAGS = -Wall -Werror
LDFLAGS = -L/home/betatest/Public/implicit-rule-archive -Wl,-rpath,'$$ORIGIN'
all : run
run : main.o libfoo.so
$(CC) $(LDFLAGS) -o $# $^
libfoo.so : CFLAGS += -fPIC # Build objects for .so with -fPIC.
libfoo.so : foo.o bar.o
$(CC) -shared -o $# $^
# Compile any .o from .c. Also make dependencies automatically.
%.o : %.c
$(CC) -c $(CFLAGS) -o $# -MD -MP $<
# Include dependencies on subsequent builds.
-include $(wildcard *.d)
.PHONY : all clean
clean :
-rm -f *.o *.d run libfoo.*
Even though I have linked -lrt in my Makefile, as you can see below, I am still getting undefined reference to 'mq_open'. Please help!
all:get1 iserv1
get: get1.c
gcc -Wall -o get1 get1.c -lrt
iserv: iserv1.c
gcc -Wall -o iserv1 iserv1.c -lrt
clean:
rm -fr *~ get1 iserv1
Note -lrt should be at end not inbetween.
Your makefile is wrong
all:get1 iserv1
get: get1.c
gcc -Wall -o get1 get1.c -lrt
all has a prerequisite of get1 and iserv1. But you created a get target and an iserv target. So e.g. get1 will be compiled with the default make rules, which does not include -lrt (this should show if you look at the gcc commands that actually are executed.)
Your makefile should like like this:
all:get1 iserv1
get1: get1.c
gcc -Wall -o get1 get1.c -lrt
iserv1: iserv1.c
gcc -Wall -o iserv1 iserv1.c -lrt
clean:
rm -fr *~ get1 iserv1