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I think I have done it for the code but simulation gives xx or zz. I couldn't do it for simulation part. Also, I'm not able to find where the error can be caused.My aim is to obtain simulation on Verilog Manchester decoder and Manchester encoder. In codes,"me_tf" is represented as encoder's testbench. My error part is that I got error from the testbench part.
At me_tf testbench part, at this line which is setup_time = clock_period/4 ; Error: Syntax error near "=" , Also it says setup_time is an unknown type. Therefore, it says also in same part #(3 * clock_period - setup_time) din = 8'hff ; at this line setup_time is declared.
module me_tf ;
reg [7:0] din ;
reg rst ;
reg clk ;
reg wr ;
wire mdo ;
wire ready ;
me u1 (rst,clk,wr,din,ready,mdo) ;
initial begin
rst = 1'b0 ;
clk = 1'b0 ;
din = 8'h0 ;
wr = 1'b0 ;
me.clk1 = 1'b0 ;
me.count = 3'b0 ;
end
integer me_chann ;
initial begin
me_chann = $fopen("me.rpt") ;
$timeformat(-9,,,5) ;
end
parameter clock_period = 10 ;
setup_time = clock_period/4 ;
always #(clock_period/2) clk = ~clk ;
initial begin
$fdisplay(me_chann, "Verilog simulation of Manchester encoder\n\n:);
$shm_open("me.shm") ;
$shm_probe("AS") ;
$fmonitor(me_chann,"%ime=%t,rst=%b,wr=%b,me.clk=%b,din=%h,me.count=%b,mdo=%b,ready=%b",$time,rst,wr,clk,me.clk1,din,me.count,mdo,ready) ;
#5 rst = 1'b1;
#15 rst = 1'b0 ;
#(3 * clock_period - setup_time) din = 8'hff ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'haa ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'h00 ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'hf0 ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'h0f ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(100 * clock_period) ;
$fdisplay (me_chann,"\nSimulation of Manchester encoder complete.");
$finish ;
end
Related
I am using Verilog to set up FPGA so that it blinks an LED once per second. And this is one way to do it:
`default_nettype none
module pps(i_clk, o_led);
parameter CLOCK_RATE_HZ = 12_000_000;
input wire i_clk;
output wire o_led;
reg [23:0] counter;
initial counter = 0;
always #(posedge i_clk)
if (counter < CLOCK_RATE_HZ/2 - 1)
begin
counter <= counter + 1'b1;
end
else
begin
counter <= 0;
o_led <= !o_led;
end
endmodule
Now I wrote this makefile:
file_v = pps
file_pcf = icebreaker
file_cpp = driver
module_top = pps
all:
yosys -p "synth_ice40 -top $(module_top) -blif $(file_v).blif" $(file_v).v
arachne-pnr -d 5k -P sg48 -o $(file_v).asc -p $(file_pcf).pcf $(file_v).blif
icepack $(file_v).asc $(file_v).bin
flash:
iceprog $(file_v).bin
simulate:
verilator --trace -Wall -cc $(file_v).v
make -C obj_dir -f V$(file_v).mk
g++ \
-I /usr/share/verilator/include/ \
-I obj_dir/ \
/usr/share/verilator/include/verilated.cpp \
/usr/share/verilator/include/verilated_vcd_c.cpp \
$(file_cpp).cpp \
obj_dir/V$(file_v)__ALL.a \
-o $(file_v).elf
./$(file_v).elf
gtkwave $(file_v).vcd
#################################################################################################
.PHONY: clean
clean:
#rm *.bin
#rm *.blif
#rm *.asc
#rm -r obj_dir
#rm *.elf
#rm *.vcd
First two makefile targets (all & flash) work flawlesly, and when bitstream file is uploaded to the board, LED flashes at 1Hz. Nice.
But, when I try to simulate this module, I run makefile target simulate, and I get an error:
┌───┐
│ $ │ ziga > ziga--workstation > 003--pps
└─┬─┘ /dev/pts/13
└─> make simulate
verilator --trace -Wall -cc pps.v
%Error-PROCASSWIRE: pps.v:72: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): o_led
%Error: Exiting due to 1 error(s)
%Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Co`
Can somebody explain what is wrong? The design already works on hardware (!), so why wouldn't my simulation compile? How do I make this example also work for the simulation?
As your error message states, it is illegal to make a procedural assignment to a wire. A procedural assignment is an assignment made inside an always block, for example. You declared o_led as a wire, but then you assigned to it in an always block. You should use a reg type inside an always block. Refer to IEEE Std 1800-2017, section 10.4 Procedural assignments.
Change:
output wire o_led;
to:
output reg o_led;
wire types are used for continuous assignments, using the assign keyword, for example.
Currently I have a cross bar in my design and I am wiring up several different modules at various offsets (xbarAWADDR and others increment by either 32 or 40 or 4 or 1 depending on the bus name). I am passing the cross bar signals to he various modules as shown below. This got me thinking though, is there a more readable or efficient way to write this many many times?
The issue I am running into is that because its AXI, the bus lengths vary as do the inputs and outputs. I thought maybe having two structures would work, but I think it would be harder to offset things like the address and data lines and may end up with more code. But I do this on average 5 to 10 times. It's massive and can get to be a pain. Maybe a virtual task that takes four structure inputs, an iteration number, and outputs two new structures?
Maybe there is some construct I am not aware of that can better do this?
For extra clarification, what I'd like to do is something like
localBusAssign( crossbarAxiBus, regBus, 0 );
localBusAssign( crossbarAxiBus, bramBus, 1);
instead of this
// Map CTRL REGS
wire [ 39: 0 ] ctrlRegAWADDR ;
wire [2 : 0 ] ctrlRegAWPROT ;
wire ctrlRegAWVALID ;
wire ctrlRegAWREADY ;
wire [31 : 0 ] ctrlRegWDATA ;
wire [3 : 0 ] ctrlRegWSTRB ;
wire ctrlRegWVALID ;
wire ctrlRegWREADY ;
wire [ 1 : 0 ] ctrlRegBRESP ;
wire ctrlRegBVALID ;
wire ctrlRegBREADY ;
wire [ 39: 0 ] ctrlRegARADDR ;
wire [ 2 : 0 ] ctrlRegARPROT ;
wire ctrlRegARVALID ;
wire ctrlRegARREADY ;
wire [31 : 0 ] ctrlRegRDATA ;
wire [1 : 0 ] ctrlRegRRESP ;
wire ctrlRegRVALID ;
wire ctrlRegRREADY ;
//ctrl reg mappings
assign ctrlRegAWADDR = xbarAWADDR[39 : 0];
assign ctrlRegAWPROT = xbarAWPROT[ 2 : 0];
assign ctrlRegAWVALID = xbarAWVALID[0];
assign xbarAWREADY[0] = ctrlRegAWREADY;
assign ctrlRegWDATA = xbarWDATA[31 : 0];
assign ctrlRegWSTRB = xbarWSTRB[3 : 0];
assign ctrlRegWVALID = xbarWVALID[0];
assign xbarWREADY[0] = ctrlRegWREADY;
assign xbarBRESP[1 : 0] = ctrlRegBRESP;
assign xbarBVALID[0] = ctrlRegBVALID;
assign ctrlRegBREADY = xbarBREADY[0];
assign ctrlRegARADDR = xbarARADDR[39 : 0];
assign ctrlRegARPROT = xbarARPROT[2 : 0];
assign ctrlRegARVALID = xbarARVALID[0];
assign xbarARREADY[0] = ctrlRegARREADY;
assign xbarRDATA[31 : 0] = ctrlRegRDATA;
assign xbarRRESP[1 : 0] = ctrlRegRRESP;
assign xbarRVALID[0] = ctrlRegRVALID;
assign ctrlRegRREADY = xbarRREADY[0];
wire [39 : 0] bramCtrlAWADDR ;
wire [2 : 0] bramCtrlAWPROT ;
wire bramCtrlAWVALID ;
wire bramCtrlAWREADY ;
wire [31 : 0] bramCtrlWDATA ;
wire [3 : 0] bramCtrlWSTRB ;
wire bramCtrlWVALID ;
wire bramCtrlWREADY ;
wire [1 : 0] bramCtrlBRESP ;
wire bramCtrlBVALID ;
wire bramCtrlBREADY ;
wire [39 : 0] bramCtrlARADDR ;
wire [2 : 0] bramCtrlARPROT ;
wire bramCtrlARVALID ;
wire bramCtrlARREADY ;
wire [31 : 0] bramCtrlRDATA ;
wire [1 : 0] bramCtrlRRESP ;
wire bramCtrlRVALID ;
wire bramCtrlRREADY ;
assign bramCtrlAWADDR = xbarAWADDR[79 :40];
assign bramCtrlAWPROT = xbarAWPROT[ 5 : 3];
assign bramCtrlAWVALID = xbarAWVALID[0];
assign xbarAWREADY[1] = bramCtrlAWREADY;
assign bramCtrlWDATA = xbarWDATA[63 :32];
assign bramCtrlWSTRB = xbarWSTRB[7 : 4];
assign bramCtrlWVALID = xbarWVALID[1];
assign xbarWREADY[1] = bramCtrlWREADY;
assign xbarBRESP[3 : 2] = bramCtrlBRESP;
assign xbarBVALID[1] = bramCtrlBVALID;
assign bramCtrlBREADY = xbarBREADY[1];
assign bramCtrlARADDR = xbarARADDR[79 :40];
assign bramCtrlARPROT = xbarARPROT[5 : 3];
assign bramCtrlARVALID = xbarARVALID[1];
assign xbarARREADY[1] = bramCtrlARREADY;
assign xbarRDATA[63 :32] = bramCtrlRDATA;
assign xbarRRESP[3 : 2] = bramCtrlRRESP;
assign xbarRVALID[1] = bramCtrlRVALID;
assign bramCtrlRREADY = xbarRREADY[1];
For whoever needs it, this is the solution I came up with.
package axiutils;
import sysdefs_lib::*;
typedef struct {
reg [ A_AXIF_WIDTH*NUMIFACE-1 : 0 ] AWADDR ;
reg [ NUMIFACE*3-1 : 0 ] AWPROT ;
reg [ NUMIFACE-1 : 0 ] AWVALID ;
reg [ NUMIFACE-1 : 0 ] AWREADY ;
reg [ A_DATA_WIDTH*NUMIFACE-1 : 0 ] WDATA ;
reg [ NUMIFACE*4-1 : 0 ] WSTRB ;
reg [ NUMIFACE-1 : 0 ] WVALID ;
reg [ NUMIFACE-1 : 0 ] WREADY ;
reg [ NUMIFACE*2-1 : 0 ] BRESP ;
reg [ NUMIFACE-1 : 0 ] BVALID ;
reg [ NUMIFACE-1 : 0 ] BREADY ;
reg [ A_AXIF_WIDTH*NUMIFACE-1 : 0 ] ARADDR ;
reg [ NUMIFACE*3-1 : 0 ] ARPROT ;
reg [ NUMIFACE-1 : 0 ] ARVALID ;
reg [ NUMIFACE-1 : 0 ] ARREADY ;
reg [ A_DATA_WIDTH*NUMIFACE-1 : 0 ] RDATA ;
reg [ NUMIFACE*2-1 : 0 ] RRESP ;
reg [ NUMIFACE-1 : 0 ] RVALID ;
reg [ NUMIFACE-1 : 0 ] RREADY ;
} xbarRegIface;
typedef struct {
logic [A_AXIF_WIDTH-1 : 0 ] AWADDR ;
logic [2 : 0 ] AWPROT ;
logic AWVALID ;
logic AWREADY ;
logic [A_DATA_WIDTH-1 : 0 ] WDATA ;
logic [3 : 0 ] WSTRB ;
logic WVALID ;
logic WREADY ;
logic [1 : 0 ] BRESP ;
logic BVALID ;
logic BREADY ;
logic [A_AXIF_WIDTH-1 : 0 ] ARADDR ;
logic [2 : 0 ] ARPROT ;
logic ARVALID ;
logic ARREADY ;
logic [A_DATA_WIDTH-1 : 0 ] RDATA ;
logic [1 : 0 ] RRESP ;
logic RVALID ;
logic RREADY ;
} axiLiteIface;
`define xbarData(liteIface, xbarIface, i) \
begin \
assign liteIface.AWADDR = xbarIface.AWADDR[(i+1)*(A_AXIF_WIDTH-1) : A_AXIF_WIDTH*i] ; \
assign liteIface.AWPROT = xbarIface.AWPROT[ 3*i+1 : 3*i] ; \
assign liteIface.AWVALID = xbarIface.AWVALID[i] ; \
assign xbarIface.AWREADY[i] = liteIface.AWREADY ; \
assign liteIface.WDATA = xbarIface.WDATA[(i+1)*(A_DATA_WIDTH-1) : A_DATA_WIDTH*i] ; \
assign liteIface.WSTRB = xbarIface.WSTRB[4*i+3 : 4*i] ; \
assign liteIface.WVALID = xbarIface.WVALID[i] ; \
assign xbarIface.WREADY[i] = liteIface.WREADY ; \
assign xbarIface.BRESP[2*i+1 : 2*i] = liteIface.BRESP ; \
assign xbarIface.BVALID[i] = liteIface.BVALID ; \
assign liteIface.BREADY = xbarIface.BREADY[i] ; \
assign liteIface.ARADDR = xbarIface.ARADDR[(i+1)*(A_AXIF_WIDTH-1) : A_AXIF_WIDTH*i] ; \
assign liteIface.ARPROT = xbarIface.ARPROT[3*i+1 : 3*i] ; \
assign liteIface.ARVALID = xbarIface.ARVALID[i] ; \
assign xbarIface.ARREADY[i] = liteIface.ARREADY ; \
assign xbarIface.RDATA[(i+1)*(A_DATA_WIDTH-1) : A_DATA_WIDTH*i] = liteIface.RDATA ; \
assign xbarIface.RRESP[2*i+1 : 2*i] = liteIface.RRESP ; \
assign xbarIface.RVALID[i] = liteIface.RVALID ; \
assign liteIface.RREADY = xbarIface.RREADY[i] ; \
end
endpackage : axiutils
Then include the package and use like this
import axiutils::*;
xbarRegIface xbarReg;
axiLiteIface bus1, bus2, bus3;
`xbarData(bus1, xbarReg, 0);
`xbarData(bus2, xbarReg, 1);
`xbarData(bus3, xbarReg, 2);
Does anyone know the Verilog code to select single register from the register list depending on the address of the register?
For Example
+------+--------------+---------+
| Name | Offset_value | Address |
+------+--------------+---------+
| Reg1 | 01 | 0x00 |
| Reg2 | 00 | 0x04 |
| Reg3 | 00 | 0x08 |
| Reg4 | 00 | 0x0C |
+------+--------------+---------+
If I give address as 0x08, then I can read/write from Reg3 and so on.
Each register is 32 bits.
From your description you have multiple flip-flops or registers that you want to update based on a write address.
always #(posedge clk) begin
case ( address )
8'h00 : Reg1 <= data;
8'h04 : Reg2 <= data;
endcase
end
If however you wanted to uses memory structure instead of REG1/2/3
reg [7:0] Reg_dat [0:254]; //255 8bit locations
always #(posedge clk) begin
Reg_dat[address] <= data;
end
As #Morgan suggested, you can use flop based memory to make reg bank,
reg [7:0] Reg_dat [0:254]; //255 8bit locations
always #(posedge clk) begin
Reg_dat[write_reg_address] <= wr_reg;
end
For writing particular reg, you have to provide write_reg_address and value which you want to be write in register.
For reading of specific register value, you have to provide only read_reg_address and it gives value of that particular reg.
assign read_reg = Reg_dat[read_reg_address];
I can't understand this piece of code below because I'm not 100% understanding the concept of semaphores. Can you explain to me what is happening in this code? Specifically with the wait() and signal() functions?
Shared Data
semaphore mutexR , mutexW, writePending , readBlock , writeBlock;
int readCount , writeCount ;
mutexR = 1 , mutexW = 1 , writePending = 1 ,
readBlock = 1 , writeBlock = 1 ;
readCount = 0 , writeCount = 0 ;
• Writer Processes
wait (mutexW ) ;
writeCount++:
if ( writeCount == 1 ) {
wait ( readBlock ) ;
}
signal (mutexW ) ;
wait ( write Block ) ;
/∗ Do Writing /Make Reservation etc ∗/
signal ( write Block ) ;
wait (mutexW ) ;
writeCount −−;
if ( writeCount == 0 ){
signal ( readBlock ) ;
}
signal (mutexW ) ;
Reader Processes
wait ( writePending ) ;
wait ( readBlock ) ;
wait (mutexR ) ;
readCount++;
if ( readCount == 1 ){
wait ( write Block ) ;
}
signal (mutexR ) ;
signal ( readBl ock ) ;
signal ( writePending ) ;
/∗Do reading /Browse etc ∗/
wait (mutexR ) ;
readCount−−;
if ( readCount == 0 ){
signal ( write Block ) ;
}
signal (mutexR ) ;
I'm using the altera synthesizer with a 32-bit bi-directional bus :
module Test
(
inout [31:0]biBus
);
wire [31:0] biEna;
wire [31:0] biVal;
I'm wondering if there's a syntax that instead of doing this:
assign biBus [ 0 ] = biEna [ 0 ] ? biVal [ 0 ] : 1'bz;
assign biBus [ 1 ] = biEna [ 1 ] ? biVal [ 1 ] : 1'bz;
...
assign biBus [ 31 ] = biEna [ 31 ] ? biVal [ 31 ] : 1'bz;
could instead be done in 1 line, something like:
assign biBus = biEna ? biVal : *'bz;
Where each bit of the bus is assigned either biVal or hi-z based on the corresponding value of biEna. How would I specify the hi-z portion above (if it's possible?
You can do this in an always_comb or always #* block:
integer i;
for (i = 31 ; i >=0 ; i--)
if (biEna[i]) biBus[i] = biVal[i];
else biBus[i] = 1'bz;
or:
biBus = 'z; //Initialize all bits to z
for (i = 31 ; i >=0 ; i--)
if (biEna[i]) biBus[i] = biVal[i]; //Overwrite the z value for bits whose enable is 1
or if you want to keep using assign statements without an always block:
genvar i;
for (i=31 ; i>=0 ; i--)
assign biBus [ i ] = biEna [ i ] ? biVal [ i ] : 1'bz;
Just {32{1'bZ}} or 32'hZZZZZZZZ.