Assign value to a 2D array from a 2D array SystemVerilog - verilog

Question

I'm quite new with SystemVerilog, I-m trying to assign a value to a 2D array from another 2D array, but each time I compile this error appers:
Error: (vlog-13069) ../src/dadda tree/daddaTree.sv(75): near "[": syntax error, unexpected '['.
Here the code:
module daddaTree import globals ::*; (
input wire signed [24:0]PP[8],
output wire [31:0]C,
output wire [31:0]S );
// layers of the reduction tree
wire [31:0]l3[8];
wire [31:0]l2[5];
wire [20]Tout_l3;
// zero paffing of the inputs partial products
assign l3[0] = 8'b00000000 & PP[0];
assign l3[1] = 7'b0000000 & PP[1] & 1'b0;
assign l3[2] = 6'b000000 & PP[2] & 2'b00;
assign l3[3] = 5'b00000 & PP[3] & 3'b000;
assign l3[4] = 4'b0000 & PP[4] & 4'b0000;
assign l3[5] = 3'b000 & PP[5] & 5'b00000;
assign l3[6] = 2'b00 & PP[6] & 6'b000000;
assign l3[7] = 1'b0 & PP[7] & 7'b0000000; // MSB for carry of the layer
// bit with no compression
// [4:0]l2[0:4] = '{l3{[4:0][0:4]}}; ERRORS HERE
// assign l2[5][1:4] = l3[5][2:5];
// assign l2[6][2:4] = l3[6][3:6];
// assign l2[7][3:4] = l3[7][6:7];
endmodule
I can assign an entire raw of bit as assign l3[0] = 8'b00000000 & PP[0];, but when I have to assign a slice of an array to another the compiler givve me the above error.
I mean how can assign for example:
"l3 from column 0 to 4, from raw 0 to 4"
to
"l2 from column 0 to 4, from raw 0 to 4"
as an example bits [4:0] of column [0:4] of l2 should have as input bits [4:0] of column [0:4] of l3, that are zeros, or PP values received from another module, so unknwon values.
I can do the assignement manualy untill a certain point:
// bit without compression
assign l2[0][0] = l3[0][0]; // c0
assign l2[1][0] = l3[1][0]; // c1
assign l2[1][1] = l3[1][1];
assign l2[2][0] = l3[2][0]; // c2
assign l2[2][1] = l3[2][1];
assign l2[2][2] = l3[2][2];
assign l2[3][0] = l3[3][0]; // c3
assign l2[3][1] = l3[3][1];
assign l2[3][2] = l3[3][2];
assign l2[3][3] = l3[3][3];
assign l2[4][0] = l3[4][0]; // c4
assign l2[4][1] = l3[4][1];
assign l2[4][2] = l3[4][2];
assign l2[4][3] = l3[4][3];
assign l2[4][4] = l3[4][4];
assign l2[5][1] = l3[5][2]; // c5
assign l2[5][2] = l3[5][3];
assign l2[5][3] = l3[5][4];
assign l2[5][4] = l3[5][5];
but also in this case an error appears
Error (suppressible): ../src/dadda tree/daddaTree.sv(95): (vlog-2698) Index 5 into array dimension 1 of 'l2' is out of bounds.
Please someone can explain me how can I assign it?
Thanks

Answer 1

[4:0]l2[0:4] = '{l3{[4:0][0:4]}} -- what is it supposed to mean? No wonder that there is a syntax error. I guess, you wanted something like the following: assign l2[0:4][4:0] = l3[0:4][4:0] which is impossible, because you take a slice of the lower dimension here.
As for index out of bounds, l2 is declared as wire [31:0]l2[5]; where the outer index is [5], meaning [0:4]. So, when you tried to use index 5 it is out of bounds since the max is 4.
So, your only bet is to use generate for loops, for example (based on your manual code):
for(genvar i = 0; i <= 4; i++) begin: L1
for (genvar j = 0; j < i; j++) begin: L2
assign l2[i][j] = l3[i][j];
end
end
Or maybe like this:
for(genvar i = 0; i <= 4; i++) begin: L1
assign l2[i][i:0] = l3[i][i:0];
end
You have to figure out exact numbers.