I am trying to form a T flip-flop in Verilog. I am studying verilog from "Digital System Design with FPGA: Implementation using verilog and vhdl" and the code for T flip-flop is here below:
module t_flip_flop(t,clk,clr,q,qn);
input t,clk,clr;
output reg q,qn;
always #(posedge clk or negedge clr)
begin
if(clr==0)
q<=0;qn<=1;
else
q<=q^t;
qn<=~(q^t);
end
I understand the xor part that we use this because of the toggle operation. I tried to form it without using "clr", but it didn't work. (I am using "clr" as clear input which is for resetting the flip-flop). Can't I do it without using "clr"?
I tried to change code like this below:
module t_flip_flop(t,clk,q,qn);
input t,clk;
output reg q,qn;
always #(posedge clk)
if(t)
begin
q<=q^t;
qn<=~(q^t);
end
But in the simulation, I get "x" for both q and qn in Vivado. I was expecting to get the same results as the code with "clr".
The clr signal is used to properly initialize q and qn.
You declared q as a reg type. In Verilog simulations, reg is initialized to x (the "unknown" value).
Consider your code without clr. At time 0, q=x. Let's say the posedge of clk is at 10ns and t=1 at that time. The assignment:
q<=q^t;
is evaluated like:
q <= x ^ 1;
Verilog evaluates x ^ 1 as x. Since x could be 0 or 1, we don't know if the expression is 1^1 or 0^1, which means that we don't know what the result of the expression should be. This means that q will remain x for the rest of the simulation. There will be no way to change its value.
Using the clr signal fixes that problem. Typically, at the start of simulation (time=0), you would set clr=0 so that q is assigned a known value (0). That prevents the x.
Even if you didn't start with clr=0, as soon as you do set clr=0 at a later time, that will resolve the x.
All of this applies to the qn signal as well.
Related
As you can see in the cursor below, the if statement looks AFTER the transition (it sees rst = 0 and thus sets a equal to in) rather than seeing rst = 1.
BUT it can also be seen that c takes the value of a BEFORE the transition.
I am wondering why this is. Suppose you want to gate a register with an enable that is delayed on clock cycle, then you can not use if (enable_delayed) because (ideally) the falling transition will happen on the rising edge of the clock and thus not be detected in simulation.
I have not had success finding my problem online. It is hard to explain and search for. Thanks for the help.
Code:
module project_test
( input logic clk, rst,
input logic in,
output logic a,
output logic b,
output logic c
);
always#(posedge clk)
if(rst) a <= 1'b0;
else a <= in;
always#(posedge clk)
if(a) b <= a;
always#(posedge clk)
c <= a;
endmodule: project_test
My guess would be you are setting rst earlier than you think and it is already 0 when the logic inside the module observes the positive clk edge.
If you were to set rst to 0 as a result of a #(posedge clk) things would work as you expect, but I suspect rst is being changed in parallel with clk.
When debugging this sort of thing, I always try to delay the assignment of the values. That is, in your module here replace <= with <= #1 .
rst is a wire (an input port is a wire, at least in verilog), so value is continuously assigned to it. So when it was sampled during the positive edge of the clock, its value is already 0.
'a' on the other hand is a reg(a flipflop) so its value when it was sampled on the positive edge of the clock is still its previous value. Its value will only change 'right after the clock'. That's why 'c' still gets the previous value of 'a'.
I think that's what's happening here.
I have got two identical (by means of simulation) flip flop process in verilog.
First is just a standard description of register with asynchronous reset (CLR) and clock (SET) with data in tied to 1:
always #(posedge SET, posedge CLR)
if (CLR)
Q <= 0;
else
Q <= 1;
second one is the same as above but with second if condition for SET signal:
always #(posedge SET, posedge CLR)
if (CLR)
Q <= 0;
else if (SET)
Q <= 1;
There is no differences between these two implementations of flip-flop in simulation. But what does the verilog standard says about this cases? Should these tests be equivalent as well as their netlists after synthesis process?
The "if (SET)" in your second example is redundant and would be optimized away n synthesis. Since the always block will only be entered on a posedge of SET or CLR, the else statement implies that a posedge of SET has occurred.
Incidentally, the first example is a much more accepted version for coding flip flops. I've yet to see the second version make it into a shipping design.
I was trying to teach myself verilog programming from "The Verilog HDL" book by Thomas Moorby. In one of the exercises, they asked to generate a clock using structural verilog only (except for the $monitor part of course).
I tried the following:
module clock();
wor clk;
assign clk=0;
initial begin
$monitor($time,,"clk=%b", clk);
#100 $finish;
end
assign #5 clk = ~clk;
endmodule
Problem is, it works in iVerilog 0.9.7, but for version 10.0 and above, it does not work.. I simply get undefined value for clk!
Does not seem like a bug in iVerilog, otherwise it would probably have been fixed in one of the 10.x releases. Is there any other way to get this working? Also, what is wrong with the current code (if any) ?
this is a messy code you have. usually clock generation done with regs as one of the following
reg clk;
initial begin
clk = 0;
forever
#5 clk = ~clk;
end
or
always
#5 clk = ~clk;
initial
clk = 0;
Strange code, you are resolving clk drives using an or-gate behaviour. First assign is constantly driving 0. Second assign is inverting the resolved value. But what is the initial value of the second wor input? Wouldn't that second assign produce X in the first place (X ored with 0 would give you X)? Have your tried running it in the simulator or at least drawing somewhere what hardware do you want to get? It's like you're feeding and inverter with 0 or'ed with X which will produce X.
If you want to model a clock you can:
1) convert first assign into initial begin clk = 0; end
2) second assign to always
3) make clk reg type
If you want a synthesizable clock generator you would require a source of oscillations, PLL, etc.
So, im trying to synthesize my verilog code to send data from ps2 keybord ->fpga->vga. Just for the background of the code, I want to press the button "1", and that to appear on the center of the screen (called the display_area)
I realised that something is not working as expected.
After carefull debugging, i realised that the problem lies in the module that converts the parallel data bus from the rom, into serial output, to assign a value in each pixel.
The code itself is pretty simple, im just providing as much info as i can.
We need a positive edge of the clock to enter the always area (or a reset). If the value display_area_enable is 1, we activate a counter from 7 till 0 (8 cycles) to index the data from the rom.
However, on the first clock, if the display area becomes 1 the exact moment when the vga_clk pulse becomes 1, the counter gets the value as it should, but the one_bit_output (the output of the module) doesnt. One_bit_output gets its first correct value the 2nd time that the always block is accessed. as a result we need 9 cycles to access an 8 bit bus.
I ll provide the code and a modelsim testbench
module shifter(reset,char_rom_data_out,vga_clk,display_area_enable,one_bit_output,counter);
input [7:0]char_rom_data_out;
input vga_clk,display_area_enable,reset;
output reg one_bit_output;
output reg [2:0]counter;
always #(posedge vga_clk or posedge reset)
begin
if (reset)
begin
counter=3'd7;
one_bit_output=0;
end
else if (display_area_enable==1)
begin
one_bit_output<=(char_rom_data_out[counter]==1);
counter<=counter-1;
end
else if (display_area_enable==0)
begin
counter<=3'd7;
one_bit_output<=0;
end
end
endmodule
module testbz();
reg reset,vga_clk,display_area_enable;
reg [7:0]char_rom_data_out;
wire [2:0] counter;
wire one_bit_output;
shifter dignitas(reset,char_rom_data_out,vga_clk,display_area_enable,one_bit_output,counter);
initial
begin
reset<=1; char_rom_data_out<=8'b11110001; vga_clk<=0;display_area_enable=0; //sto 10 skaei o prwtos kyklos, kai meta ana 20
#5 reset<=0; display_area_enable<=0;
#5 display_area_enable<=1;
#160 display_area_enable<=0;
end
always
begin
#10 vga_clk=~vga_clk;
end
endmodule
and the simulation is :
Can someone explain to me why on the first pulse of the vga_clk, the output is not expected?
Change one_bit_output so that it does not change in relation to the clock edge, but asynchronously in relation to the display_area_enable. The counter keeps track of which element to output. This is essentially a multiplexer with display_area_enable as the selector, or more likely an AND gate with one input being display_area_enable.
As toolic said, the synchronous one_bit_output cannot change on the same cycle as its activating signal. This is because of the set-up times of the flip-flops, the signal must be stable for some time before the clock edge. Now, if you are using one_bit_output to drive some flip-flop, then it MUST update on the next edge. Don't try to avoid this by using latches, that will make synthesis quite hard.
module shifter(reset,char_rom_data_out,vga_clk,display_area_enable,one_bit_output,counter);
input [7:0]char_rom_data_out;
input vga_clk,display_area_enable,reset;
output reg one_bit_output;
output reg [2:0]counter;
always #(posedge vga_clk or posedge reset)
begin
if (reset)
begin
counter<=3'd7;
//one_bit_output<=0;
end
else if (display_area_enable==1)
begin
//one_bit_output<=(char_rom_data_out[counter]==1);
counter<=counter-1;
end
else if (display_area_enable==0)
begin
counter<=3'd7;
//one_bit_output<=0;
end
end
assign one_bit_output = display_area_enable ? char_rom_data_out[counter] : 0;
endmodule
I'm attempting to write a specific version of the D Flip Flop that uses NOR gates only:
Following is gate level diagram:
The code I'm using in Verilog:
module DFlipFlop(D,CLK,Q,QN);
input D, CLK;
output Q, QN;
reg Q, QN, R, S;
always #(negedge CLK) begin
R = ~(~(~(D|S)|R)|CLK);
S = ~(~(D|S)|R|CLK);
Q = ~(R|QN);
QN = ~(S|Q);
end
endmodule
I then uploaded the compiled program to a PLD and it's not flip flopping and I cannot figure out why. I've tried many different things already.
Note that I have to use the 4 equations in my program for R, S, Q, and QN.
Your problem is the following line:
always #(negedge CLK) begin
What your circuit is actually creating is a seperate flip flop for each of R, S, QN, and Q., since you've declared tnis block as being edge-triggered (that's what negedge CLK means). If you want a purely combinational circuit (like what your gate-level diagram shows) you should be using an always #(*) block instead.
Note that Quartus II has a helpful tool called the RTL Viewer (Tools->Netlist Viewers->RTL Viewer) which shows a block-level schematic of your synthesised circuit. If you look at that, you'll see that you're actually creating four flip-flops (and some logic) with your code, not one.