How to loop for a variable amount in verilog? - verilog

Question

In any hardware definition language, I know we can't declare a loop to loop over some circuits for some variable n times, instead we need to loop for a fixed value.
So I wanted to ask, if I have the following snippets of code:
I'm writing some sort of pseudocode in verilog, and this is an unfinished code.
input [7-1:0] note_switch;
reg[7-1:0] varnum[7-1:0];
reg[7-1:0] limit;
wire[7-1:0] numofhigh_switch;
check_high test (numofhigh_switch, note_switch);
always#(posedge octave) begin
if(octave) begin
for(count = 0; count < numofhigh_switch; count = count + 1) begin
varnum[numofhigh_switch + count] <= varnum[count] << 7;
end
end else begin
for(count = 0; count < numofhigh_switch; count = count + 1) begin
varnum[numofhigh_switch + count] <= varnum[numofhigh_switch + count];
end
end
end
I wanted to make something resembling like this, but again I know this will not work in a hardware description language, so how should I write so I can get the effect of rolling the for loop?

Answer 1

Actually, synthesis tools need to statically determine the maximum possible number of loops, not just a fixed number. You can do this a number of ways
Put the maximum into the conditional expression
for(count = 0; count < numofhigh_switch && count < 8; count = count + 1) begin
varnum[numofhigh_switch + count] <= varnum[count] << 7;
end
Use a conditional branching statement inside the loop
for(count = 0; count < 8; count = count + 1)
if (count < numofhigh_switch) begin
varnum[numofhigh_switch + count] <= varnum[count] << 7;
end
In SystemVerilog you can use a break statement.
for(count = 0; count < 8; count = count + 1) begin
if (count >= numofhigh_switch) break;
varnum[numofhigh_switch + count] <= varnum[count] << 7;
end