Output port continuous assignment problem - verilog

Question

I have the code below, which is an array of shift registers connected to each other.
i.e., Sin->sr1->sr2->...sr14->sr15->sr16->Sout.
module Array #(
parameter NCOL = 4,
parameter NROW = 4
)
(
input clk,
input reset,
input Sin,
output Sout
);
// NCOL * NROW shift registers
wire [NCOL - 1: 0] shift_reg [NROW - 1: 0];
genvar i, j;
/* Connected array of SRs */
generate
for (j = 0; j < NCOL; j=j+1) begin: sr_y
for (i = 0; i < NROW; i=i+1) begin: sr_x
sr sr_inst (
.clk(clk),
.reset(reset),
.Sin(shift_reg[i][j]),
.Sout(shift_reg[i+1][j])
);
end
end
// connect 4th SR in each column to the 1st SR in the next column
for (j = 0; j < NCOL - 1; j=j+1) begin: shift_y
assign shift_reg[0][j+1] = shift_reg[NROW-1][j];
end
endgenerate
/* Connect the shift register endpoints to the input and output of the module */
assign shift_reg[0][0] = Sin;
assign Sout = shift_reg[NROW-1][NCOL-1];
endmodule
module sr #(parameter WIDTH = 16)(
input clk,
input reset,
input Sin,
output Sout
);
reg [WIDTH-1:0] sr_data;
reg sout; /* Latched shift register output */
always #(posedge clk) begin
if (reset) begin
sr_data <= 16'd0;
end else begin
sr_data[0] <= Sin;
sr_data[WIDTH-1:1] <= sr_data[WIDTH-2:0];
end
end
always #(negedge clk) begin
if (reset == 1'b1) begin
sout <= 1'b0;
end else begin
sout <= sr_data[WIDTH-1];
end
end
assign Sout = sout;
endmodule
I got some errors (below) when trying to compile. I have declared the ports as wires, but I still have the same problem. Could you help solve the errors as I can't seem to see the issue?
warning: ignoring out of bounds l-value array access shift_reg[4].
error: Output port expression must support continuous assignment.
: Port 6 (Sout) of sr is connected to shift_reg[(i)+('sd1)][j]

Answer 1

You declared the signal as:
wire [NCOL - 1: 0] shift_reg [NROW - 1: 0];
When you plug in the parameter values, this resolves to:
wire [3:0] shift_reg [3:0];
This is an array of 4 elements (0 to 3), each of which is 4 bits wide.
The problem is this line inside the for loops:
.Sout(shift_reg[i+1][j])
When i is set to its maximum value of 3 in the loop, i+1 is 4, which resolves to:
.Sout(shift_reg[4][j])
But, there is no shift_reg[4] element of the array. That explains the warning message. You are selecting an element which is not in the array ("out of bounds").
I don't understand the error message, but I suspect it will go away if you fix the code that produces the warning.