Is it possible to see if vivado inferred blockram? - vivado

Question

I have a following piece of code:
module cw305_reg_aes #(
parameter pADDR_WIDTH = 21,
parameter pBYTECNT_SIZE = 14,
parameter pPK_WIDTH = 800 // 800 * 8
)(
input wire usb_clk,
input wire crypto_clk,
input wire [pADDR_WIDTH-pBYTECNT_SIZE-1:0] reg_address,
input wire [pBYTECNT_SIZE-1:0] reg_bytecnt,
output reg [7:0] read_data,
input wire [7:0] write_data,
input wire reg_read,
input wire reg_write,
output wire [7:0] reg_pk
);
reg [7:0] reg_read_data;
reg [7:0] reg_crypt_public_key [pPK_WIDTH-1:0];
(* ASYNC_REG = "TRUE" *) reg [7:0] reg_crypt_public_key_crypt [pPK_WIDTH-1:0];
always #(posedge crypto_clk) begin
for (i=0; i<pPK_WIDTH;i=i+1) begin
reg_crypt_public_key_crypt[i] <= reg_crypt_public_key[i];
end
end
assign reg_pk = reg_crypt_public_key_crypt[0]
always #(*) begin
if (reg_read) begin
case (reg_address)
`REG_CRYPT_PUBLIC_KEY: reg_read_data = reg_crypt_public_key[reg_bytecnt];
default: reg_read_data = 0;
endcase
end
else
reg_read_data = 0;
end
always #(posedge usb_clk) begin
if (reg_write) begin
case (reg_address)
`REG_CRYPT_PUBLIC_KEY: reg_crypt_public_key[reg_bytecnt] <= write_data;
endcase
end
end
How can I see if Vivado 2021.1 inferred block ram instead of distributed ram for the reg_crypt_public_key array?

Answer 1

Block rams are reported in the synthesis log. If BRAMs are inferred there will be a section detailing what parts of the HDL produced which BRAMs of how many ports, width, etc
It reads like the log mentioned on the forums here: https://support.xilinx.com/s/article/61027?language=en_US
With header like
|Module Name ------ | RTL Object | PORT A (depth X width) | W | R | PORT B (depth X width) | W | R | OUT_REG | RAMB18 | RAMB36 | Hierarchical Name
Additionally opening the final utilization report will show a hierarchical break down of where in the design is using BRAMs vs LUTs as memory (distributed).
Finally see the synthesis guide for how to intentionally infer BRAM per the manufacturers recommended code guidelines. p. 111 https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2021_2/ug901-vivado-synthesis.pdf

Answer 2

Another way:
Open the post route design or dcp file in the Vivado GUI.
Locate the netlist window and surf the hierarchical path to expected BRAM path.
Right click 'schematic' on the design element in the netlist window.
The schematic viewer opens showing: inferred BRAM, distributed RAM or registers.
Here is a little example showing a register connected to a BRAM:
This is a general way you can explore what the tools have done with the RTL code.