Facing Some problem is FSM design and datapath [duplicate] - verilog

Question

The output waveform shows no change in the sum, dif, burrow, and out. Even after increasing delay time, still the output shows no change. This should work like the mod adder like add 10 and 2 and with mod 3 give output zero.
CODE
module Mod_adder(a,b,p,out);
input [3:0] a;
input [3:0] b;
input [3:0] p;
output [3:0] out;
wire [3:0] sum;
wire cout;
wire burrow;
wire [3:0] dif;
ripple_carry_adder r1(a,b,sum,cout,1'b0);
ripple_carry_adder r2(sum,~p,dif,burrow,1'b1);
repeat_sum rs1(dif,burrow,sum);
outval o1(sum,burrow,out);
endmodule
module full_adder(in0, in1, cin, out, cout);
input in0, in1, cin;
output out, cout;
assign out = in0 ^ in1 ^ cin;
assign cout = ((in0 ^ in1) & cin) | (in0 & in1);
endmodule
module ripple_carry_adder(in0, in1, out, cout,cin);
input [3:0] in0;
input [3:0] in1;
output [3:0] out;
output cout;
input cin;
wire c1, c2, c3;
full_adder fa0(in0[0], in1[0], cin, out[0], c1);
full_adder fa1(in0[1], in1[1], c1, out[1], c2);
full_adder fa2(in0[2], in1[2], c2, out[2], c3);
full_adder fa3(in0[3], in1[3], c3, out[3], cout);
endmodule
module repeat_sum(dif,burrow,sum);
input [3:0] dif;
input burrow;
output [3:0] sum;
assign sum = (burrow == 1'b0) ? dif:sum;
endmodule
module outval(sum,burrow,out);
input [3:0] sum;
input burrow;
output [3:0] out;
assign out = (burrow == 1'b1) ? sum:out;
endmodule
TEST BENCH
` include "MOD_ADDER.V"
module Mod_adder_tb;
reg [3:0] a;
reg [3:0] b;
reg [3:0] p;
wire [3:0] out; // wires
// Instantiate the module to be tested
Mod_adder MA1(a,b,p,out);
initial begin // initial block
$dumpfile("Test_Full_Adder.vcd");
$dumpvars(1, MA1);
a=4'b1010;
b=4'b0100;
p=4'b0011;
#100;
end // end of initial block
endmodule

Answer 1

I see 2 major problems.
Your out testbench signal is unknown (X) because of driver contention. For example, the sum signal in Mod_adder has multiple drivers: from the r1 instance and from the rs1 instance. The out output of r1 and the sum output of rs1 are both driving the sum wire. You should not drive the same signal from 2 different module instances. You could rename one of the sum signals to something unique, like sum_rs1 and declare a new wire.
wire [3:0] sum, sum_rs1;
Also, you have combinational feed back loops. For example:
assign out = (burrow == 1'b1) ? sum:out;
The out signal should not be on both the LHS and RHS of a continuous assignment.