Serial-Load-Shift-Register - verilog

Question

In the serial load shift register, how can i make sure that the shift was not disabled before at least five data has been loaded?
module serial_load_shift_register(
input logic clk ,
input logic shift_enable,
input logic d_in ,
output logic q
);
logic [0:4] register;
always #(posedge clk) begin
register[0] <= shift_enable ? d_in : register[0];
register[1] <= shift_enable ? register[0] : register[1];
register[2] <= shift_enable ? register[1] : register[2];
register[3] <= shift_enable ? register[2] : register[3];
register[4] <= shift_enable ? register[3] : register[4];
end
assign q = register[4];
endmodule: serial_load_shift_register

Answer 1

What you can do is put the shift_enable signal into a shift register as well that gives you a history of that signal. If that register is non-zero, use that condition to control the shifting of data.
module serial_load_shift_register(
input logic clk ,
input logic shift_enable,
input logic d_in ,
output logic q
);
logic [0:3] register;
always #(posedge clk) begin
logic [0:4] enable;
enable = {enable,shift_enable};
if (enable != 0) register <= {register, d_in};
end
assign q = register[0];
endmodule: serial_load_shift_register
Note that the assignment to enable is not using an NBA. This means the statements that references enable following the assignment use the current value, not the value from the previous cycle. There are no issues with race conditions because I declared enable local to the always block, so no one can reference it outside the always.

Answer 2

There are several ways to do it. In general you need a kind of a counter which will be used to keep your enable alive for a number of cycles. As an example, you can have another register which shifts the value of the enable signal for 5 cycles or so. Here is an example.
module serial_load_shift_register(
input logic clk ,
input logic reset,
input logic shift_enable,
input logic d_in ,
output logic q
);
logic [4:0] register;
logic [4:0] enable_validator;
always #(posedge clk) begin
if (reset) begin
enable_valida <= 0;
register <= 0;
end
else begin
enable_valid <= (enable_valid << 1) | shift_enable;
if (|enable_valid) begin
register <= (register << 1) | d_in;
end
end
end
assign q = register[4];
endmodule: serial_load_shift_register
In the above example enable_valid is such a register. It keeps enable flag alive while any of its bits is non-zero, allowing the register to keep shifting even if the enable_shift signal disappears.
I did a couple of updates to your code. First, I added a 'reset' which is needed to initialize some values. Also, I replaced your bit-by-bit shift with a shift operator <<.
You just need to figure out timing relation between different signals in your model and tune the code up to your needs.
Here is a sample test bench to quick test of the above.
module tb;
logic clk, reset, shift_enable, d_in, q;
serial_load_shift_register shifter(.clk(clk), .reset(reset), .shift_enable(shift_enable), .d_in(d_in), .q(q));
initial begin
clk = 0;
forever #2 clk = !clk;
end
initial begin
reset = 0;
d_in = 0;
shift_enable = 0;
#4 reset = 1;
#4 reset = 0;
#4 d_in = 1;
#4 shift_enable = 1;
#8 shift_enable = 0;
d_in = 0;
#30 $finish;
end
always #* begin
$display("%0t> clk %b, shift_enable = %b, d_in = %b, q ==> %b (%b %b)", $time, clk, shift_enable, d_in, q,
shifter.enable_validator, shifter.register);
end
endmodule