FSM is double incrementing - verilog

Question

I have a newbie FSM Verilog question. In the below code, around line 96, I am incrementing led_num with the non blocking led_num <= led_num+1; However, because of the way my code is setup I have a non blocking curr_state <= next_state at line 82, and then I am doing a next_state <= "NEXT STATE" in every one of my case statements. This is causing me to be in each state 2 clocks and is causing my led_num <= led_num+1 to execute twice, and I want just a single time.
How do I go about fixing this so I am in each state a single clock or how do I prevent the led_num being incremented by two each time? I had one person tell me to non blocking all of the time, but some examples mix them and I am pretty sure I need to move my nextState to use a blocking assignment but I have tried several things so far and I keep messing it up.
`timescale 1ns / 1ps
module ws2812_b(clk, rst, send_the_data, led_data_out);
input clk;
input rst;
input send_the_data;
output reg led_data_out;
parameter NUMBER_LEDS = 5;
parameter ADDRESS_BITS =8;
parameter NUM_BITS = 24;
parameter STATE_BITS = 4;
parameter T0_HIGH_0_COUNT = 6; // .35us (System clock = 12Mhz, 83.3 ns/cycle.
parameter T0_HIGH_1_COUNT = 16; // .9us
parameter CYCLE_COUNT = (T0_HIGH_0_COUNT+T0_HIGH_1_COUNT); //.9+.35
parameter RESET_COUNT = 1500; // 50us
localparam ST_IDLE = 4'd0,
ST_GET_WORD = 4'd1,
ST_SEND_START = 4'd2,
ST_UPDATE_WORD = 4'd3,
ST_DELAY_0 = 4'd4,
ST_DRIVE_0 = 4'd5,
ST_DELAY_1 = 4'd6,
ST_CHECK_WORD_DONE = 4'd7,
ST_SEND_RESET = 4'd8,
ST_NDEF_9 = 4'd9,
ST_NDEF_10 = 4'd10,
ST_NDEF_11 = 4'd11,
ST_DELAY_1S = 4'd12,
ST_NDEF_13 = 4'd13,
ST_NDEF_14 = 4'd14,
ST_NDEF_15 = 4'd15;
reg [STATE_BITS-1:0]currState;
reg [STATE_BITS-1:0]nextState;
reg [14:0] delay_value;
reg [NUM_BITS-1:0] led_word;
reg [5:0] bit_num;
reg [13:0] delay0, delay1;
reg [8:0] led_num;
`define rundelay currState <= ST_DELAY_1S
`define returndelay currState <= nextState
always #(posedge clk, posedge rst)
begin
if (rst) begin
currState <= ST_IDLE;
nextState <= ST_IDLE;
led_data_out <=0;
led_word <= 0;
bit_num <= 0;
delay0 <= 0;
delay1 <=0;
delay_value <=0;
led_num <= 0;
end
else
begin
currState <= nextState;
case (currState)
ST_IDLE: //0
begin
led_data_out <= 0;
nextState <= ST_GET_WORD;
led_num <= 0;
end
ST_GET_WORD: //1
begin
led_word <= 24'h335599;
bit_num <= 0;
nextState <= ST_SEND_START;
led_num <= led_num + 1 ; // ***** DOUBLE INCREMENTS ****
end
ST_SEND_START: //2
begin
led_data_out <= 1;
if (led_word[0]==1)
begin
delay0 <= T0_HIGH_1_COUNT;
delay1 <= (CYCLE_COUNT - T0_HIGH_1_COUNT + 1);
end else
begin
delay0 <= T0_HIGH_0_COUNT;
delay1 <= (CYCLE_COUNT - T0_HIGH_0_COUNT + 1);
end
nextState <= ST_UPDATE_WORD;
end
ST_UPDATE_WORD: //3
begin
led_word[23:0] <= {1'b0,led_word[23:1]};
bit_num <= bit_num+1;
nextState <= ST_DRIVE_0;
delay_value <= delay0;
`rundelay;
end
ST_DRIVE_0: //5
begin
led_data_out <= 0;
nextState <= ST_CHECK_WORD_DONE;
delay_value <= delay1;
`rundelay;
end
ST_CHECK_WORD_DONE: //4
begin
if (bit_num<24)
begin
nextState <= ST_SEND_START;
end else
begin
if (led_num<3)
begin
nextState <= ST_GET_WORD;
end else
begin
nextState <= ST_SEND_RESET;
end
end
end
ST_SEND_RESET:
begin
led_data_out <= 0;
nextState <= ST_IDLE;
delay_value <= 2000;
`rundelay;
end
ST_DELAY_1S: // Delay of ~1sec. Note that the total delay is one clock cycle more because of the state transition.
begin
if (delay_value)
begin
delay_value <= delay_value -1; // as long as delay_value is larger than zero ( bitwise or)
// decrement (decrementing counters synthesize smaller than
// incrementing counters as no comparator is needed, only a
// zero check which is a bitwise or.
currState <= currState;
end
else
begin
//currState <= nextState; // if it hits zero ; throw the target state into currentstate.
`returndelay;
end
end
default:
begin
currState <= ST_IDLE;
end
endcase
end
end
endmodule

Answer 1

As Greg pointed out, FSMs are implemented one of two ways:
Single always block (like you've implemented) In this case, every clock runs through the "always block" once and you only need one "State" variable. All variables are "non-blocking" ("<=" symbol) which implies that all statements are executed in parallel.
Double always blocks. In this case, the first always block is purely combinational, which is fully "blocking" assigns so that you can have sequential arithmetic to calcuate your final value. The second always block behaves like a set of registers to let the whole state-machine "step" to the next state on the clock edge. This setup requires "currState" and "nextState". The first combinational always block calculates "nextState" from "currState". The second (sequential) always block simply transfers nextState to currState on a clock edge.
In your case, it looks like you're trying to jump to a "delay" state for a certain number of cycles and then jump back to the next state in the sequence like a subroutine in C code that delays.
While I haven't run it, I think the following is closer to what you're trying to do. When you jump to ST_DELAY_1S, you need to save the state you want to return to in a separate variable (I used afterDelayState) so that you can spin in the delay state and then return (much like the instruction pointer on the stack) to the proper place.
`timescale 1ns / 1ps
module ws2812_b(clk, rst, send_the_data, led_data_out);
input clk;
input rst;
input send_the_data;
output reg led_data_out;
parameter NUMBER_LEDS = 5;
parameter ADDRESS_BITS =8;
parameter NUM_BITS = 24;
parameter STATE_BITS = 4;
parameter T0_HIGH_0_COUNT = 6; // .35us (System clock = 12Mhz, 83.3 ns/cycle.
parameter T0_HIGH_1_COUNT = 16; // .9us
parameter CYCLE_COUNT = (T0_HIGH_0_COUNT+T0_HIGH_1_COUNT); //.9+.35
parameter RESET_COUNT = 1500; // 50us
localparam ST_IDLE = 4'd0,
ST_GET_WORD = 4'd1,
ST_SEND_START = 4'd2,
ST_UPDATE_WORD = 4'd3,
ST_DELAY_0 = 4'd4,
ST_DRIVE_0 = 4'd5,
ST_DELAY_1 = 4'd6,
ST_CHECK_WORD_DONE = 4'd7,
ST_SEND_RESET = 4'd8,
ST_NDEF_9 = 4'd9,
ST_NDEF_10 = 4'd10,
ST_NDEF_11 = 4'd11,
ST_DELAY_1S = 4'd12,
ST_NDEF_13 = 4'd13,
ST_NDEF_14 = 4'd14,
ST_NDEF_15 = 4'd15;
reg [STATE_BITS-1:0] State;
reg [STATE_BITS-1:0] afterDelayState;
reg [14:0] delay_value;
reg [NUM_BITS-1:0] led_word;
reg [5:0] bit_num;
reg [13:0] delay0, delay1;
reg [8:0] led_num;
//`define rundelay currState <= ST_DELAY_1S
//`define returndelay currState <= nextState
always #(posedge clk, posedge rst)
begin
if (rst) begin
State <= ST_IDLE;
afterDelayState <= ST_IDLE;
led_data_out <=0;
led_word <= 0;
bit_num <= 0;
delay0 <= 0;
delay1 <=0;
delay_value <=0;
led_num <= 0;
end
else
begin
case (State)
ST_IDLE: //0
begin
led_data_out <= 0;
State <= ST_GET_WORD;
led_num <= 0;
end
ST_GET_WORD: //1
begin
led_word <= 24'h335599;
bit_num <= 0;
State <= ST_SEND_START;
led_num <= led_num + 1 ; // ***** DOUBLE INCREMENTS ****
end
ST_SEND_START: //2
begin
led_data_out <= 1;
if (led_word[0]==1)
begin
delay0 <= T0_HIGH_1_COUNT;
delay1 <= (CYCLE_COUNT - T0_HIGH_1_COUNT + 1);
end else
begin
delay0 <= T0_HIGH_0_COUNT;
delay1 <= (CYCLE_COUNT - T0_HIGH_0_COUNT + 1);
end
State <= ST_UPDATE_WORD;
end
ST_UPDATE_WORD: //3
begin
led_word[23:0] <= {1'b0,led_word[23:1]};
bit_num <= bit_num+1;
State <= ST_DRIVE_0;
delay_value <= delay0;
// delay "delay0" cycles and then jump to ST_DRIVE_0
delay_value <= delay0;
State <= ST_DELAY_1S;
afterDelayState <= ST_DRIVE_0;
end
ST_DRIVE_0: //5
begin
led_data_out <= 0;
// delay "delay1" cycles and then jump to ST_CHECK_WORD_DONE
delay_value <= delay1;
State <= ST_DELAY_1S;
afterDelayState <= ST_CHECK_WORD_DONE;
end
ST_CHECK_WORD_DONE: //4
begin
if (bit_num<24)
begin
State <= ST_SEND_START;
end else
begin
if (led_num<3)
begin
State <= ST_GET_WORD;
end else
begin
State <= ST_SEND_RESET;
end
end
end
ST_SEND_RESET:
begin
led_data_out <= 0;
// delay 2000 cycles and then jump to ST_IDLE
delay_value <= 2000;
State <= ST_DELAY_1S;
afterDelayState <= ST_IDLE;
end
// This is a special "delay" loop that jumps to a specified "afterDelayState" when the delay_value runs to zero
ST_DELAY_1S: // Delay of ~1sec. Note that the total delay is one clock cycle more because of the state transition.
begin
if (delay_value)
begin
// every clock cycle stay in the ST_DELAY_1S state until the "delay_value" runs to zero
delay_value <= delay_value -1; // as long as delay_value is larger than zero ( bitwise or)
// decrement (decrementing counters synthesize smaller than
// incrementing counters as no comparator is needed, only a
// zero check which is a bitwise or.
//
// no change in State, so we stay here
// State <= State
end
else
begin
//after it hits zero, jump to the state we stored in afterDelayState
State <= afterDelayState;
end
end
default:
begin
State <= ST_IDLE;
end
endcase
end
end
endmodule
In the code above, each state has only one State <= (new state) command.
We only assign the afterDelayState variable when jumping to the ST_DELAY_1S "subroutine" so we know where to go back to.
I took out the `defines to make all assignments more explicit.
One side recommendation is to install VSCode and iverilog so that you can do syntax checking, auto-formatting and compile checking inside the editor. This quickly helped me clean things up.