Resolving a warning in verilog: read after blocking assignment in same process - verilog

Question

I've this code which is throwing some warning messages which I'm trying to resolve.
module someModuleName(...)
...
...
reg [3:0] i;
wire [3:0] onstate_count;
wire [3:0] ack_count;
reg [3:0] j;
bit switchState;
always #(*) begin :EVAL_ACK
switchState = 1'b0;
for (i = 0; i < onstate_count; i = i+1) begin
if (onStateControls[i] == 1'b1) begin
switchState = 1'b1;
end
end
for (j = 0; j < ack_count; j = j+1) begin
if (ack_expression_type[j] == 1'b0) begin
if (switchState) begin
ack[j] = ack_logic_value[j];
end else begin
ack[j] = !ack_logic_value[j];
end
end else begin
ack[j] = ack_logic_value[j];
end
end
end
endmodule
The warning mesage I'm getting is:
Warning-[SM_TPL] Transaction path loss after synthesis
In module 'someModuleName', transaction path through signal 'i' will be
lost after synthesis due to read after blocking assignment in same process.
-
Warning-[SM_TPL] Transaction path loss after synthesis
In module 'someModuleName', transaction path through signal 'switchState' will be
lost after synthesis due to read after blocking assignment in same process.
-
Warning-[SM_TPL] Transaction path loss after synthesis
In module 'someModuleName', transaction path through signal 'j' will be
lost after synthesis due to read after blocking assignment in same process.
I tried making i, j as integer and genvar but no effect, I'm new to verilog and don't know how to resolve this warning.
Any help would be highly appreciated.
Thanks.

Answer 1

Synthesizers require loops to static unroll.
A loop must be able to static unroll to be synthesizable.
Using a snip it from your original code:
switchState = 1'b0;
for (i = 0; i < onstate_count; i = i+1) begin // <-- onstate_count is not a compile time constant, therefore cannot static unroll
if (onStateControls[i] == 1'b1) begin
switchState = 1'b1;
end
end
The equivalent synthesizer friendly version would be:
switchState = 1'b0;
for (i = 0; i < 16; i = i+1) begin // <-- loop is static
if (i < onstate_count) begin // <-- condition check
if (onStateControls[i] == 1'b1) begin
switchState = 1'b1;
end
end
end
A similar change needs to be made to for (j = 0; j < ack_count; j = j+1). The ack also needs to be assigned a value for indexes greater than ack_count or it will infer a latches; and most FPGA synthesizers do not support latches.

Answer 2

Try this code. Also are onstate_count and ack_count variables constants?
module someModuleName(...)
...
...
genvar i,j;
wire [3:0] onstate_count;
wire [3:0] ack_count;
bit switchState;
generate
for (i = 0; i < onstate_count; i = i+1) begin
always #(*) begin :EVAL_ACK
switchState = 1'b0;
if (onStateControls[i] == 1'b1) begin
switchState = 1'b1;
end
end
end
endgenerate
generate
for (j = 0; j < ack_count; j = j+1) begin
always #(*) begin
if (ack_expression_type[j] == 1'b0) begin
if (switchState) begin
ack[j] = ack_logic_value[j];
end else begin
ack[j] = !ack_logic_value[j];
end
end else begin
ack[j] = ack_logic_value[j];
end
end
end
endgenerate
endmodule