I have designed a simple sequence detector that works, but I am wondering how I can edit it so that the valid_password outputs as high for 3 clock cycles regardless of input changes.
Here is what I've set my valid_password as:
assign valid_password = (present_state==s8)&(pass_in==3);
I know I've set it so that it only outputs high for this one specific state and input value but I am very new to this so any advice for recommended syntax's I should look for is very appreciated.
Try a delay register. Here trigger register will assert high when valid_password condition hits. This is then passed on for two cycles.
reg [2:0] trigger;
always#(posedge clk or negedge rstn)
begin
if(!rstn)
trigger <= 'd0;
else
begin
trigger[0] <= (present_state==s8) & (pass_in==3);
trigger[1] <= trigger[0];
trigger[2] <= trigger[1];
end
end
assign valid_password = ( (present_state==s8)&(pass_in==3) ) | trigger[0] | trigger[1] | trigger[2];
Related
I have a question about using timers and clocks in Verilog. I want to set up a custom reg to compare to an accumulator, which will control the state of an LED. The board uses inverse logic, so 0 is high on the LED. There are a few concepts I just need some clarification on. The clock is 100 MHz.
always #(posedge clk100 or negedge reset_)
begin
cust_LED_counter <= (cust_LED_counter<cust_LED_timer) ? cust_LED_counter + 1'b1 : 16'd0;
cust_LED_timer1 <= (cust_LED_counter == cust_LED_timer);
if(!reset_)
begin
cust_LED1 <= 'b0;
cust_LED_timer <= 'd0;
cust_LED_timer1 <= 'd0;
end
else
begin
cust_LED1 <= ~cust_LED_timer1;
end
end
For the accumulator, what is the action that resets it and allows for blinking to happen? Would it not hit the cust_LED_timer value and stay at that high reading?
I think I'm misunderstanding how a FPGA clock operates. Assuming this would cause a blinking action in the LED, it would mean some timer hit the upper limit and reset; however, I'm not sure if this would take place in the counter portion of the code, or instead would occur where the clock/reset is defined.
Also, based on how this layout looks it wouldn't be a uniform blink, in terms of equal time on and off. Is there a way to implement such a system for custom input?
Here's a simple module that should blink the LED with a 50-50 duty cycle for an arbitrary number of clocks (up to 2^26)
module blink(input clk, input rst, input [25:0] count_max, output LED);
reg [25:0] counter, next_count;
assign LED = counter < count_max >> 1;
always #(posedge clk or posedge rst)
begin
if (rst)
counter <= 0;
else
counter <= next_count;
end
always #* begin
if (counter < count_max - 1)
next_count = counter + 1;
else
next_count = 0;
end
endmodule // blink
Let me know if this doesn't compile! I don't have a verilog compiler where I'm writing this from at the moment!
module clks(
input clk,
output [15:0] led
);
wire div2, div4, div8;
reg [2:0] count = 0;
assign div2 = count[0];
assign div4 = count[1];
assign div8 = count[2];
always #(posedge clk) count = count + 1;
endmodule
How can I turn on each led (I have 15 leds) using clock?
I'm really having trouble finding helpful resources online
initial begin
case({count})
2'b00:
led = 15'b000000000000001;
2'b01:
led = 15'b000000000000010;
...
endcase
end
This didn't work.
Or could I do something like this?
led = led + 1;
In your sample code above, you defined count as 3 bits, but your case statements are 2 bits wide. Also, you don't want the initial statement, rather use an always statement.
always # (count)
begin
case(count)
3'b000 : led = 15'b000_0000_0001;
3'b001 : led = 15'b000_0000_0010;
...
endcase
end
I guess that 'by using clock' means changing the led every clock cycle, right? Also it looks like you are trying to encode the led sequentially. In this case you can do the following:
you need to reset your lead to an initial value, sey 15'b1;
every clock cycle you can just shift it left by one. You should not do it in an initial block (though there is a technical way to do so). Use always blocks:
Here is an example:
module clks(
input clk,
input reset,
output reg [15:0] led
);
always #(posedge clk) begin
if (reset == 1)
led <= 15'b1;
else
led <= led << 1;
end
endmodule
In the above case '1' will travel through all bits of led over 15 clock cycles once. 'led' will become '0' after this. You have to make sure that it becomes '1' again if you want to continue in cycles.
Another possibility is to initialize 'led' in the always block, but it is not always synthesizable. YOu do not need a reset signal here.
initial led = 15'b1;
always #(posedge clk) led <= led << 1;
I'm trying to make a morse code display using an led. I need a half second pulse of the light to represent a dot and a 1.5 second pulse to represent a dash.
I'm really stuck here. I have made a counter using an internal 50MHz clock on my FPGA. The machine I have to make will take as input a 3 bit number and translate that to a morse letter, A-H with A being 000, B being 001 and so on. I just need to figure out how to tell the FPGA to keep the led on for the specified time and then turn off for about a second (that would be the delay between a dot pulse and a dash pulse).
Any tips would be greatly appreciated.
Also, it has to be synthesizable.
Here is my code. It's not functioning yet. The error message it keeps giving me is:
Error (10028): Can't resolve multiple constant drivers for net "c3[0]"
at part4.v(149)
module part4 (SELECT, CLK, CLOCK_50, RESET, led);
input [2:0]SELECT;
input RESET, CLK, CLOCK_50;
output reg led=0;
reg [26:0] COUNT=0; //register that keeps track of count
reg [1:0] COUNT2=0; //keeps track of half seconds
reg halfsecflag=0; //goes high every time half second passes
reg dashflag=0; //goes high every time 1 and half second passes
reg [3:0] code; //1 is dot and 0 is dash. There are 4 total
reg [1:0] c3; //keeps track of the index we are on in the code.
reg [3:0] STATE; //register to keep track of states in the state machine
reg done=0; //a flag that goes up when one morse pulse is done.
reg ending=0; //another flag that goes up when a whole morse letter has flashed
reg [1:0] length; //This is the length of the morse letter. It varies from 1 to 4
wire i; // if i is 1, then the state machine goes to "dot". if 0 "dash"
assign i = code[c3];
parameter START= 4'b000, DOT= 4'b001, DASH= 4'b010, DELAY= 4'b011, IDLE=
4'b100;
parameter A= 3'b000, B=3'b001, C=3'b010, D=3'b011, E=3'b100, F=3'b101,
G=3'b110, H=3'b111;
always #(posedge CLOCK_50 or posedge RESET) //making counter
begin
if (RESET == 1)
COUNT <= 0;
else if (COUNT==8'd25000000)
begin
COUNT <= 0;
halfsecflag <= 1;
end
else
begin
COUNT <= COUNT+1;
halfsecflag <=0;
end
end
always #(posedge CLOCK_50 or posedge RESET)
begin
if (RESET == 1)
COUNT2 <= 0;
else if ((COUNT2==2)&&(halfsecflag==1))
begin
COUNT2 = 0;
dashflag=1;
end
else if (halfsecflag==1)
COUNT2= COUNT2+1;
end
always #(RESET) //asynchronous reset
begin
STATE=IDLE;
end
always#(STATE) //State machine
begin
done=0;
case(STATE)
START: begin
led = 1;
if (i) STATE = DOT;
else STATE = DASH;
end
DOT: begin
if (halfsecflag && ~ending) STATE = DELAY;
else if (ending) STATE= IDLE;
else STATE=DOT;
end
DASH: begin
if ((dashflag)&& (~ending))
STATE = DELAY;
else if (ending)
STATE = IDLE;
else STATE = DASH;
end
DELAY: begin
led = 0;
if ((halfsecflag)&&(ending))
STATE=IDLE;
else if ((halfsecflag)&&(~ending))
begin
done=1;
STATE=START;
end
else STATE = DELAY;
end
IDLE: begin
c3=0;
if (CLK) STATE=START;
else STATE=IDLE;
end
default: STATE = IDLE;
endcase
end
always #(posedge CLK)
begin
case (SELECT)
A: length=2'b01;
B: length=2'b11;
C: length=2'b11;
D: length=2'b10;
E: length=2'b00;
F: length=2'b11;
G: length=2'b10;
H: length=2'b11;
default: length=2'bxx;
endcase
end
always #(posedge CLK)
begin
case (SELECT)
A: code= 4'b0001;
B: code= 4'b1110;
C: code= 4'b1010;
D: code= 4'b0110;
E: code= 4'b0001;
F: code= 4'b1011;
G: code= 4'b0100;
H: code= 4'b1111;
default: code=4'bxxxx;
endcase
end
always #(posedge CLK)
begin
if (c3==length)
begin
c3<=0; ending=1;
end
else if (done)
c3<= c3+1;
end
endmodule
I have been reading your code and there are many issues:
The code is not formatted.
You did not provide a test-bench. Did you write one?
"Can't resolve multiple constant drivers for net" Search on stack exchange for the error message. It has been asked many times.
Use always #(*) not e.g. always #(STATE) you are missing signals like i, halfsecflag, ending. But see point 6: You want the STATE in a clocked section.
Where you use always #(posedge CLK) you must use non-blocking assignments: <=.
There are many places where you use always #(posedge CLK) where you want to use always #(*) (e.g. where you set length and code) Opposite you want to use a posedge CLK where you work with your STATE.
Use one clock and one clock only. Do not use CLK and CLOCK_50. Use either one or the other.
Take care of your vector sizes. This 8'd25000000 is wrong as you can no fit 25000000 in 8 bits.
Your usage of halfsecflag is excellent! I have see many times where people think they can use always #(halfsecflag) which is a recipe for disaster!
Below you find a small piece of your code which I have re-written.
All assignments are non-blocking <=
halfsecflag is essential to operate the code only every half a second, so I put that by itself in a separate if at the top. I would use that throughout the code.
All register are reset, both COUNT2 and dashflag.
dashflag was set to 1 but never set back to 0. I fixed that.
I specified the vector sizes. It makes the code "Lint proof".
Here is it:
always #(posedge CLOCK_50 or posedge RESET)
begin
if (RESET == 1'b1)
begin
COUNT2 <= 2'd00;
dashflag <= 1'b0;
end // reset
else if (halfsecflag) // or if (halfsecflag==1'b1)
begin
if (COUNT2==2'd2))
begin
COUNT2 <= 2'd0;
dashflag <=1'b1;
end
else
begin
COUNT2 <= COUNT2+2'd1;
dashflag <=1'b0;
end
end // clocked
end // always
Start fixing the rest of your code the same way. Write a test-bench, simulate and trace on a waveform display where things go wrong.
Normally you would build the finite state machine to produce the output. That machine would have some stages, like reading the input, mapping it to a sequence of morse code element, shifting out the elements to output buffer, waiting for conditions to move to the next morse element. You will need some timer that would produce one morse time unit intervals, and depending on the FSM stage you will wait one, three or seven time units. The FSM will spin in the waiting stage, it doesn't "magically" sleeps in some fpga-produced delay, there's no such things.
Okay a year later, I know exactly what one should do if they want to create a delay in their verilog program! Essentially, what you should do is create a timer using one of the clocks on your FPGA. For me on my Altera DE1-SoC, the timer I could use is the 50MHz clock known as CLOCK_50. What you do is make a timer module that triggers on the positive (or negative, doesn't matter) edge of the 50MHz clock. Set up a count register that holds a constant value. For example, reg [24:0] timer_limit = 25'd25000000; This is a register that can hold 25 bits. I've set this register to hold the number 25 million. The idea is to flip a bit every time the value in this register is exceeded. Here's some pseudocode to help you understand:
//Your variable declarations
reg [24:0] timer_limit = 25'd25000000; //defining our timer limit register
reg [25:0] timer_count = 0; //See note A
reg half_sec_clock;
always#(posedge of CLOCK_50) begin
if timer_count >= timer_limit then begin
reset timer_count to 0;
half_sec_clock = ~half_sec_clock; //toggle your half_sec_clock
end
Note A: Setting it to zero may or may not initialize count, it's always best to include a reset function that clears your count to zero because you don't know what the initial state is when you're dealing with hardware.
This is the basic idea of how to introduce timing into your hardware. You need to use an onboard clock on your device, trigger on the edge of that clock and create your own slower clock to measure things like seconds. The example above will give you a clock that triggers periodically every half second. For me, this allowed me to easily make a morse code light that could flash on either 1 half second count, or 3 half seconds. My best advice to you beginners is to work in a modular fashion. For example build your half second clock and then test it out to see if you can get a light on your FPGA to toggle once every half second (or whatever interval you want). :) I really hope this is the answer that helps you. I know this is what I was looking for when I originally posted this question so long ago.
So I'm trying to implement a counter that takes a one-clock-cycle enable and starts counting from there. It sends a one-clock-cycle expired once the counter finishes counting. The enable will never be sent again until the counter is done counting, and the value input is continuous.
I was thinking of just using a reg variable that is changed to high when enable = 1, and changed to low once the counter finishes counting. I fear this may imply latches that I don't want... is there a better way to do this?
current code:
module Timer(
input [3:0] value,
input start_timer,
input clk,
input rst,
output reg expired
);
//counter var
reg [3:0] count;
//hold variable
reg hold;
//setting hold
always #*
begin
if (start_timer == 1'b1)
hold <= 1'b1;
end
//counter
if (hold == 1'b1)
begin
always # (posedge(clk))
begin
if(count == value - 1)
begin
expired <= 1'b1;
count <= 4'b0;
hold <= 1'b0;
end
else
count <= count + 1'b1;
end
end
endmodule
Well, you seem to be on the right track, but you are correct that your current design will imply latches. You can fix this by making hold its own flipflop and only counting when its set as you have done, clearing it once your counting is complete. Note this will impact the timing of your system, so you have to make sure everything happens on the correct cycle. Its hard to say from your description whether you want expired to be set on the "value"th cycle or "value + 1"th cycle. In order to show you a few of what youll need to do to your code to get it to compile and have the proper timing, Im going to assume a few things:
value is held at a constant number and doesnt not change while counting
expired will pulse on the valueth clock after start_timer is set
value will not be 4'h0 (though this is easy to deal with, as no counting is required based on assumption 1)
So, your module would look like this:
module Timer(
input [3:0] value,
input start_timer,
input clk,
input rst,
output expired
);
//counter var
reg [3:0] count;
//hold variable
reg hold;
// Note you cannot assign hold from multiple blocks, so the other one has been removed
// In order to meet the timing from assumption 2, we need to combinationally determine expired (be sure we only set it while we are counting; thus the dependence on hold)
assign expired = (count == value - 4'd1) && (hold == 1'b1);
//counter
// Note, you cannot have logic outside of a procedural block!
always #(posedge clk) begin
if ((hold == 1'b0) && (start_timer == 1'b1)) begin
hold <= 1'b1; // Hold is part of the register, making it its own flipflop
count <= 4'd0;
end
else if (hold == 1'b1) begin
if (count == value - 4'd1) begin
hold <= 1'b0; // Clear hold, we are done counting
// No need to clear count, it will be cleared at the start of the timer
end
else begin
count <= count + 4'd1;
end
end
end
endmodule
Can't find anything on this, it doesn't fit in well with keywords. Somewhere I came across a statement that it's bad practice to put some things in an always block sensitivity list. Things other than clk and other related internal signals within the device can, according to the statement, cause routing inefficiencies.
I find it convenient when coding relatively slow applications to generate subdivided clock signals, and use these in always blocks.
For Example:
reg Counter [12:0] ;
reg SlowClk ;
always # (posedge clk)
begin
Counter <= Counter + 13'h1 ;
SlowClk <= Counter[12] ;
end
always # (posedge SlowClk)
Note: My text entry has one statement per line, if the lines are concatenated in the final post, that's due to the website.
Is there anything wrong with this?
Yes this is indeed a bad practice. So you can do something different to get the SlowClk edge.
You can take a wire, to detect the SlowClk positive edge.
wire got_SlowClk_posedge;
Now to detect, SlowClk, positive edge, you need to have it's current and next clock values (Current Clock Value should be 0 & Next Clock Value should be 1) But fortunately, in your case, SlowClk, next clock value is the current value of Counter[12]. So you can use it.
assign got_SlowClk_posedge = Counter[12] & ~SlowClk;
So now your 2nd always block may look like this :
// Instead of #(posedge SlowClk)
always #(posedge clk)
begin
if(got_SlowClk_posedge)
begin
// Your code for positive edge of SlowClk
end
end
Nothing is wrong in this. If design required divided clock we must have to do this.
but best practice is to use en signal for clock divider so that you can use same clock in every always block. And yes its good to use reset in clcok diveder
(any sequential ckt required reset).
reg Counter [12:0] ;
reg SlowClk ;
reg div_clk ;
wire en;
always # (posedge clk)
begin
if(!reset)
Counter <= 13'h0;
else
Counter <= Counter + 13'h1;
end
assign en = (Counter ==13'h0)? 1'b1 : 1'b0;
always # (posedge clk)
begin
if(!reset)
div_clk = 1'b0;
else(en)
div_clk <= ~div_clk;
end