Is a timescale or any other directive mandatory in Verilog (2001) or is its use a matter of convention or style? For example, I typically use default_nettype none to enforce explicit net declarations throughout my implementation. However, Verilog does not require me to do so.
When it comes to timescale, I obviously place it at the top of my HDL testbench. But why use it in every single module of an IP? In case of inconsistent definitions, could this lead to more problems rather than preventing them?
Generally speaking, Verilog compiler directives are not mandatory.
For timescale, refer to IEEE Std 1800-2017, section 22.7 `timescale:
If there is no timescale specified or it has been reset by a `resetall
directive, the default time unit and precision are tool-specific.
The directives are global in scope, which means that when the compiler encounters one, it remains in effect for all the following code which is compiled (until another is encountered). So, there is no need to add timescale directives to all your code.
However, in practice, I have seen compilers generate errors if the 1st module (or modules) compiled does not have a timescale directive but subsequent modules do. These simulators also offer a command-line option to set the default timescale to avoid this error.
Related
Trying to model a 74245 with delays representative of the HCT device.
I am finding that the timings I'm providing in a specify block are not respected.
I have added an extra route A->C (not part of my orig design) to illustrate that the delays can work, just not where there are conditionals in the expression ie none of the other delays are effective.
If I put a delay inline on the assign then this is always respected.
My code is here : https://www.edaplayground.com/x/hDa
Any ideas?
I am a noob.
It was an icarus bug and it's just been fixed on master.
https://github.com/steveicarus/iverilog/issues/315#issuecomment-607800126
Thanks all
I am getting a warning that says [Synth 8-3332] Sequential element (\i_data_1_vect_1_reg[31] ) is unused and will be removed from module cg_top in vivado. But the simulation is working fine. I would be great if someone shares why these warnings occur even though I am using these registers and how to solve it.
There are two possibilities:
The register is not needed and hence can be removed. The most common reasons for that are:
The output is not used.
The output always has the same value and can be replaced with a constant 1 or 0.
There is another (often adjacent) register which always has the same value and thus the output of that one is replicated.
Unfortunately there are some rare cases where Vivado reports removal, but actually nothing is removed. The only way to find out for certain is to open the synthesised design and check the schematic (visually, which may take you a long time) if the register has indeed been removed.
As I said these are rare cases. if your are inexperienced with HDL my money is that the register really is not needed.
Whatever the message, I have always found that the actual generated logic was correct.
Is it syntax correct with gate level Verilog file, where the the sub-modules are defined after the owning module or they should be defined before? Does it matter according to Verilog rules?
Regards,
This might be compiler dependent, but if you are using a tool that supports SystemVerilog (which most commercial tools do these days), it should be syntactically correct to define modules in any order, perhaps even in separate files.
See IEEE Std 1800-2012, Section 3.12 for more info.
Notice that after compilation, there is another step which is called elaboration. At that point all the module description should have been compiled correctly. From SystemVerilog LRM:
Compilation is the process of reading in SystemVerilog source code, decrypting encrypted code, and analyzing the source code for syntax
and semantic errors. Implementations may execute compilation in one or
more passes. Implementations may save compiled results in a
proprietary intermediate format, or may pass the compiled results
directly to an elaboration phase. Not all syntax and semantics can be
checked during the compilation process. Some checking can only be done
during or at the completion of elaboration.
SystemVerilog supports both single file and multiple file compilation
through the use of compilation units (see 3.12.1).
Elaboration is the
process of binding together the components that make up a design.
These components can include module instances, program instances,
interface instances, checker instances, primitive instances, and the
top level of the design hierarchy. Elaboration occurs after parsing
the source code and before simulation; and it involves expanding
instantiations, computing parameter values, resolving hierarchical
names, establishing net connectivity and in general preparing the
design for simulation.
The short answer is that you can forward-reference modules in Verilog; this has always been the case, and is not tool-dependent (in other words, you can do it in either order). There may be complications if you use libraries and configurations but, in general, you can assume that you can instantiate a module before it is defined.
In most of Verilog, you have to declare something before you reference it. There are some exceptions, including task and function calls, implicit wires, cross-module/hierarchical references, and module names. In these cases, the tool waits until elaboration to find the referenced object. There is no clear explanantion of much of this in the LRM, unfortunately. This is how Verilog-XL did it, and everyone else has done it ever since.
Note that this isn't related to 'gate-level' files.
According to the rules defined in the Verilog LRM, modules, functions and tasks are the only things that may be referenced before being declared. SystemVerilog adds interfaces and programs to that list. Verilog also has implicitly declared nets that makes it seem that you are referencing a net before it being declared, but I strongly suggest not using that feature by using the compile directive ``default_nettype none.
SystemVerilog introduced some very useful constructs to improve coding style. However, as one of my coworkers always says, "You are not writing software, you are describing hardware." With that in mind, what features of the language should be avoided when the end result needs to be synthesized? This paper shows what features are currently synthesizable by the Synopsys tools, but to be safe I think one should only use the features that are synthesizable by all of the major vendors. Also, what constructs will produce strange results in the netlist which will be difficult to follow in an ECO?
In summary: I like compact and easy to maintain code, but not if it causes issues in the back end. What should I avoid?
Edit: In response to the close vote I want to try to make this a bit more specific. This question was inspired by this answer. I am a big fan of using the 'sugar' as Dave calls it to reduce the code complexity, but not if some synthesis tools are going to mangle signal names and make the result difficult to deal with. I am looking for more examples like this.
Theoretically, if you can write software that is synthesized into machine code to run on a piece of hardware, that software can be synthesized into hardware. And conversely, there are hardware constructs in Verilog-1995 that are not considered synthesizable simply because none of the major vendors ever got around to supporting it (e.g. assign/deassign). We still have people using //synopsis translate on/off because it took so long for them to support `ifdef SYNOPSYS.
Most of what I consider to be safe for synthesis in SystemVerilog is what I call syntactic sugar for Verilog. This is just more convenient ways of writing the same Verilog code with a lot less typing. Examples would be:
data types: typedef, struct, enum, int, byte
use of those types as ports, arguments and function return values
assignment operators: ++ -- +=
type casting and bit-streaming
packages
interfaces
port connection shortcuts
defaults for function/tasks/macro arguments, and port connections
Most of the constructs that fall into this category are taken from C and don't really change how the code gets synthesized. It's just more convenient to define and reference signals.
The place it gets difficult to synthesize is where there is dynamically allocated storage. This would be class objects, queues, dynamic arrays, and strings. as well as dynamically created processes with fork/join.
I think some people have a misconception about SystemVerilog thinking it is only for Verification when in fact the first version of the standard was the synthesizable subset, and Intel was one of the first users of it as a language for Design.
SystemVerilog(SV) can be used both as a HDL (Hardware Description Language) and HVL (Hardware Verification Language) and that is why it is often termed an "HDVL".
There are several interesting design constructs in SV which are synthesizable and can be used instead instead of older Verilog constructs, which are helpful in optimizing code and achieving faster results.
enum of SV vs parameter of Verilog while modelling FSM.
Use of logic instead of reg and wire.
Use of always_ff, always_comb, always_latch in place of
single always blocks in Verilog.
Use of the unique and priority statements instead of Verilog's
full and parallel case statements.
Wide range of data types available in SV.
Now what I have discussed above are those constructs of SystemVerilog which are used in RTL design.
But, the constructs which are used in the Verification Environment are non-synthesizable. They are as follows:
Dynamic arrays and associative arrays.
Program Blocks and Clocking blocks.
Mailboxes
Semaphores
Classes and all their related features.
Tasks
Chandle data types.
Queues.
Constrained random features.
Delay, wait, and event control statements.
In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FPGAs (Altera and Xilinx in particular), but I assume the same rules would apply to ASIC design, possibly more so due to the inability to change the design after it is built.
Update 4/29/2010: I was originally thinking of synthesis and P&R (Place & Route) warnings, but the simulation warnings are valid too.
Here is my perspective from the ASIC world (99% Verilog, 1% VHDL).
We make an effort to eliminate all warnings from our log files, because in general, we interpret warnings as the tool telling us that we should not expect predictable results.
Since there are many types of tools which can generate warnings (simulation/debugger/linter/synthesis/equivalence-checking, etc.), I will focus this discussion on simulator compiler warnings.
We analyze warnings and categorize them into two main groups: ones which we deem will not affect the results of our simulation, and others which may affect the results. First, we use a tool's options to explicitly enable as many warnings as possible. For the first group, we then use a tool's options to selectively disable those warning messages. For the second group, we fix the Verilog source code to eliminate the warnings, then we promote the warnings to errors. If any warnings are later introduced in those categories, we force ourselves to fix them before we are allowed to simulate.
An exception to the above methodology is for third-party IP, whose Verilog code we are not allowed to modify.
That method works fairly well for RTL simulations, but it gets much more difficult when we run gate simulations using back-annotated SDF. There is simply not enough time to analyze and eliminate the literally millions of warnings. The best we can do is to use scripts (Perl) to parse the log files and categorize the warnings.
In summary, we try our best to eliminate the warnings, but it is not always practical to do so.
Here's what I do, for reference. I inspect all the log files from the tool(s).
For Altera Quartus II that includes the map, fit and merge reports. I also turn on the Design Rule Check (DRC) option and check that file. For some messages that are easy to fix, e.g. port missing from the instantiation or incorrect constant width, I fix them. Other ones I look into. For ones that are in the cores, e.g. a width mismatch because I'm not using the full output deliberate, I mark them to be suppressed in the .srf file. I only suppress the specific messages, not all of the "similar messages" since there may be others, either now or in the future, which are problems.
I wrote a script which applies a set of regexps to the logfile to throw away lines which I "know are OK". It helps, but you have to be a bit careful with the regexps - what did jwz say about them :)
The most important reason that I can think of is simulation-synthesis mismatch. Synthesis tools do a lot of optimizations (as they rightly should) and if you leave loopholes in your design you are asking for trouble. Refer to IEEE 1364.1-2002 for details about the synthesis standard.
There is no need to remove all warnings, but all should be reviewed. To make this possible for big designs, some warnings can be suppressed by its type or id.
For example, some synthesis tools give a warning if a Verilog parameter is defined and no value assigned during the module instantiation. For me, this warning is just an advice to use localparam. It's a good idea to suppress it by its id (e.g. LINT-01).
In some cases, I want to see the warnings and don't suppress them. For example, my tool gives a warning whenever I define a virtual clock by constraints. The warning doesn't mean there is a problem, but I can catch a missing source of a clock that wasn't intended to be virtual.
Sometimes non-existence of warnings points out a problem. For example, if I change an application variable, there should be a warning.
There are too many cases. Sometimes the warning is unavoidable. Sometimes it's nice to have warnings to be able to review some critical stuff. If the designer knows what he/she does, there is no problem.
Some warnings are expected and there is a problem if you don't get a warning.
for example if you really really want a latch but there is no warning about inferring a latch then your synthesis might not have made what you intended.
so no, you don't always want to 'deal' with all warnings.