Verilog waveform of inputs is identical, however, output is different - verilog

Question

I'm currently trying to implement an up/down counter in Verilog with dataflow modeling. While trying to add a limit to the counter (so that the counter will reset to the appropriate value when the limit is reached) I stumbled into an error. Even though the waveforms of clear_q, clear, and clear_s are the same, likewise the waveforms of preset_q, preset, and preset_s are the same, the behaviors of Q, R, and S are different, notably Q is different from R and S.
Picture of Waveforms
Of note, the rising edge of the three clear signals is not aligned with the falling edge of the clock, however, Q going from 0 to F is aligned with the rising edge of the three clear signals.
From the code, it is clear that the only difference between clear_q and clear_s, and preset_q and preset_s, is the simple inclusion of "& 1'b1". The only way that Q would go to F from 0 is if preset_q goes low and clear_q goes high momentarily, however from the waveform preset_q stays high.
The purpose of the "& 1'b1" is to temporarily simulate the equality checker commented out.
What exactly is wrong with the "& 1'b1" or is there another issue at hand?
limited_ud_counter.v
module limited_ud_counter(input clk, preset, clear, up, input[3:0] limit, output[3:0] Q);
//wire[3:0] n;
wire[3:0] Q, R, S;
wire e, preset_p, clear_p;
// assign n[0] = Q[0] ^ limit[0];
// assign n[1] = Q[1] ^ limit[1];
// assign n[2] = Q[2] ^ limit[2];
// assign n[3] = Q[3] ^ limit[3];
// assign e = !(n[0] | n[1] | n[2] | n[3]);
assign e = 0;
//(preset & clear & (!(e & up))) | (preset & !clear);
//(preset & clear & !(e & (!up))) | (clear & !preset);
assign preset_q = ((preset & clear) & 1'b1) | (preset & !clear);
assign clear_q = ((preset & clear) & 1'b1) | (clear & !preset);
assign preset_s = ((preset & clear)) | (preset & !clear);
assign clear_s = ((preset & clear)) | (clear & !preset);
//Q not showing expected behavior
up_down_counter udc0(clk, preset_q, clear_q, up, Q);
//R showing expected behavior
up_down_counter udc1(clk, preset, clear, up, R);
//S also showing expected behavior
up_down_counter udc2(clk, preset_s, clear_s, up, S);
endmodule;
up_down_counter.v
module up_down_counter(input clk, preset, clear, up, output[3:0] Q);
wire[2:0] jk_up, jk_down, jk;
wire[3:0] Q_bar;
assign jk_up[0] = Q[0] & up;
assign jk_down[0] = Q_bar[0] & (!up);
assign jk[0] = jk_up[0] | jk_down[0];
assign jk_up[1] = Q[1] & jk_up[0];
assign jk_down[1] = Q_bar[1] & jk_down[0];
assign jk[1] = jk_up[1] | jk_down[1];
assign jk_up[2] = Q[2] & jk_up[1];
assign jk_down[2] = Q_bar[2] & jk_down[1];
assign jk[2] = jk_up[2] | jk_down[2];
jkff jkff0(clk, 1'b1, 1'b1, preset, clear, Q[0], Q_bar[0]);
jkff jkff1(clk, jk[0], jk[0], preset, clear, Q[1], Q_bar[1]);
jkff jkff2(clk, jk[1], jk[1], preset, clear, Q[2], Q_bar[2]);
jkff jkff3(clk, jk[2], jk[2], preset, clear, Q[3], Q_bar[3]);
endmodule
jkff.v
module jkff(input clk, j, k, preset, clear, output q, q_bar);
wire j_p, k_p, q_m, q_bar_m;
assign j_p = !(j & q_bar & clk);
assign k_p = !(k & q & clk);
sr sr0(j_p, k_p, preset, clear, q_m, q_bar_m);
gated_sr gsr0(!clk, q_m, q_bar_m, preset, clear, q, q_bar);
endmodule;
sr.v
//set, reset, preset, clear are active low
module sr(input set, reset, preset, clear, output q, q_bar);
assign q = !(set & preset & q_bar);
assign q_bar = !(reset & clear & q);
endmodule
gated_sr.v
//enable, set, and reset are active high; preset and clear are active low
module gated_sr(input enable, set, reset, preset, clear, output q, q_bar);
wire set_p, reset_p;
assign set_p = !(set & enable);
assign reset_p = !(reset & enable);
sr sr0 (
.set (set_p),
.reset (reset_p),
.preset (preset),
.clear (clear),
.q (q),
.q_bar (q_bar)
);
endmodule
testbench code
`include "limited_ud_counter.v"
`include "../UpDownCounter/up_down_counter.v"
`include "../JKFF/jkff.v"
`include "../GatedSR/gated_sr.v"
`include "../SR/sr.v"
module limited_ud_counter_tb;
reg clk, preset, clear, up;
reg[3:0] limit;
wire[3:0] Q;
always begin
#5 clk = !clk;
end
initial begin
$dumpfile("limited_ud_counter_tb.vcd");
$dumpvars;
clk = 1'b0;
up = 1'b1;
preset = 1'b1;
clear = 1'b0;
limit = 4'b1100;
#12 clear = 1'b1;
#200 $finish;
end
limited_ud_counter ludc0(clk, preset, clear, up, limit, Q);
endmodule
This is using Icarus Verilog if that helps.

Answer 1

I've figured out the issue. What was happening was while the values of preset_q and clear_q were being computed, there was a moment where both preset_q and clear_q went low. Since these were fed into SR-latches, an error would occur.
All at the same time (t=12), preset_q and clear_q went like this:
preset_q = 1, clear_q = 0
preset_q = 0, clear_q = 0 <- this is the problem
preset_q = 1, clear_q = 1
Since these all happened at the same time, only the final values were visible on the waveform. To fix this, I chose to make both preset and clear signals go high if they were both low at the SR-latch level.