I had this problem I had to solve where I have to design a transition diagram to accept a string A, where A is any string with a substring of 101 in any position over the set {0,1} (RE of (1+0)*101(1+0)*). I solved it and designed the machine and drew it on an online tool but unfortunately the material I'm studying from does not have any written solution to this problem for me to check, so I wanted to check if my answer is correct here, since google gave me various answers none of which were like mine.
Now the idea here is that the diagram keeps going on forever, alternating between states until it encounters a consecutive input of 101, then it ends up in the final state q4, in which it's free to continue receiving whatever input until the end of the string. Is what I have done correct?
Thank you in advance.
No. Consider the string 1101. It is valid, but your machine will end in state q1 and reject it.
Related
In UML 2.5.1, the initial pseudostate of a state machine is defined as follows:
An initial Pseudostate represents a starting point for a Region; that
is, it is the point from which execution of its contained behavior
commences when the Region is entered via default activation. It is the
source for at most one Transition, which may have an associated effect
Behavior, but not an associated trigger or guard. There can be at
most one initial Vertex in a Region.
In other words, a UML state machine should almost always contain exactly one initial pseudostate, which should have exactly one outgoing transition.
However, can an initial pseudostate have incoming transitions as well? For example:
I cannot find anything forbidding it in the UML specification, yet I cannot find any example online where this case happen, therefore I was wondering whether or not I overlooked anything.
EDIT: To go into more detail, if we look into the OCL constraints stated in the specification, we can only find the following one that affects outgoing transitions (section 14.5.6.7):
inv: (kind = PseudostateKind::initial) implies (outgoing->size() <= 1)
but I cannot find any constraint regarding incoming transitions
EDIT2: I have just realized that my model is wrong! Considering this sentence of the specification (cited above): "It is the source for at most one Transition, which may have an associated effect Behavior, but not an associated trigger or guard."
Therefore the transition between init and s1 should actually have zero triggers, instead of having e1 as a trigger.
Note that while this does not invalidate the initial question.
I see nothing in the UML 2.5.1 Specification that prohibits a transition whose target is the initial pseudostate.
Such a transition would be meaningless at best and confusing at worst, which is likely why no examples are found.
Edit: see the comments!
On p. 423 UML 2.5:
15.7.18 InitialNode [Class]
15.7.18.4 Constraints
• no_incoming_edges
An InitialNode has no incoming ActivityEdges.
inv: incoming->isEmpty()
N.B. If you intend to have a self-transition for e1 then why not just using that? The Initial can anyway have only on singular outgoing edge, namely to the first state (here s1).
No this is not allowed. And why would one Do that? As you already stated in the cited text,it can only have one outgoing edge without any guard. So what is the added value, as you cannot reuse anything.
I think the text is pretty clear as-is: "[An initial Pseudostate] is the point from which execution of its contained behavior commences when the Region is entered via default activation." If you connect a transition back around to the initial psuedostate, the initial psuedostate is no longer "the point from which execution of its contained behavior commences," it is something else, and is therefore undefined.
It doesn't make sense to construct a language acceptor which does not able to accept any language. I specifically talking about FA which accept languages not transducer or translator which translate languages.
People build them all the time. You have a set of states, and each state is accessible ultimately from every other, and there is no final state, so it never halts, though it might get stuck in a cycling loop. No issue with that at all.
Do a search on "busy beaver".
The mathematical model of a FSM, as described on the wikipedia page, notes that the set F of final states may be empty. While an empty set of final states isn't much use if the FSM is used as a recogniser, FSMs can also be used as transducers.
For example, a Mealy machine doesn't include a set of final states, since it the output from the machine as the input is processed which is of interest.
It is not just that it can exist - it is even necessary: how else would one accept the empty set, which is one of the regular languages. Unless you use an automaton with unaccessible states, which is pretty similar to not having a final state.
I am new to understanding Verilog as this language requires thinking in terms of synthesis.
While doing some program I found that:
begin
buf_inm[row][col] =temp_data;
#1 mux_data=buf_inm[row][col];
end
gave correct results than
begin
buf_inm[row][col] =temp_data;
mux_data=buf_inm[row][col];
end
in terms of assignments of variables.
Can anybody explain what is the difference between these two?
In any other higher level languages construct 2 (without delay) would have given correct assignments.
Thanking you,
Yours sincerely,
R. Ganesan.
First of all #1 is a one time scale delay that you can use in simulation, but it is not synthesizeable. When you say "gave correct results", it might help if you explained what results you are seeing, but my guess is that you assigned something to the 2 dimensional vector, and then you assign that to the max_data and are expecting mux_data to be what temp data was. Is it retaining old data? Is it undefined?
That said, I would say the difference is a synthesizeable assignment versus a non-sythesizeble one. In the first case you should see two state changes separated by a timescale unit. The second case, because it is blocking, should see both values update in zero-time, and in the order as written top to bottom. If you aren't seeing that, something else is potentially at foot here. What tool are you using? Tool version? Maybe you can share your full code and test bench so we can see why your results are unexpected.
Suppose a DFA has to be designed which accept all string over Σ={0,1}* which start and ends with same symbol(e.g-0110,10101 etc.).Is ε a acceptable string ? Which means,Is start state a final state?
It depends entirely on what is meant. Human languages are vague and imprecise; that's why we invent formalisms like regular expressions in the first place.
If this is an exercise, I would ask whomever is giving you the exercise for clarification. On the surface, two interpretations seem reasonable:
The empty string does not start and end with different letters, so it should not be excluded
The empty string does not start and end with the same letter, so it should not be included
If it is an exercise and you have the original wording, you can provide a quote, but as stated, the answer is simply not clear. If homework, you could always provide two DFAs, one for each interpretation, with some discussion of the ambiguity.
If it is just a question you made up, then you will have to answer for yourself whether you want the empty string in your language.
YES.
The String ε belongs to {0,1}* and its start and end symbols are not different.So it should be accepted by the DFA
I read a paper. It states that " For data sets, we used 10 realizations for parameter selection and 20 other realizations for parameter selection.
Does realization in this case mean simulation ?
Thanks
It would be better if you provided either (i) a link to the paper or (ii) more context, because at the moment it isn't clear what the sentence refers to.
My best guess is that it means 'realization' in the sense of 'a particular series that might be generated by a specified random process'.