Consider the following SV code snippet:
module clocks();
logic a ;
bit clk =0;
initial begin
forever #1ns clk = ~clk ;
end
clocking cb#(posedge clk);
default input #1step output negedge;
output a;
endclocking
initial begin
#(cb);
#100ps;
cb.a <= 1 ;
#(cb);
#100ps;
cb.a <= 0 ;
repeat(10) #(cb);
end
endmodule
A signal changes after 100ps after the clocking block event through an output synchronous drive.
I observe a different behavior while running it with two EDA simulators.
With the first simulator, the clocking block output a acts on the second posedge, with the signal changing on the second falling edge. You can see the image below.
First simulator
On the other hand, with the second simulator, the clocking block output acts on the FIRST clock, and the effects can be seen on the first falling clock edge. You can see the image below.
Second simulator
If, on the other hand, I change the output skew delay, using a delay smaller (es 10ps) than the 100ps delay, the second simulator behaves as the first one ( the a signal changes after the second posedge with the the output skew of 10ps).
Which one of the two simulators is more compliant to the IEEE 1800-2017 SV standard ? In my opinion, according to my comprehension of the standard, the first simulator is more compliant.
The timescale is set to 1fs to avoid any issue related to simulator resolution.
The second simulator (with the unexpected negedge behavior) is VCS. I found the following information on Solvnet:
Enhanced Clocking Block Behavior When Skew is negedge/posedge By
default, VCS overrides the clocking event with the skew when the skew
is specified as posedge/negedge. However, you can use the
-ntb_opts no_cb_edge_override option to avoid overriding the clocking event at input, output, and inout. The following is the behavior of
this option at different clocking directions: • Input: Value is
sampled at the specified clocking skew delay before the clocking event
and the update happens at the clocking event. • Output: The output is
updated at the specified clocking skew delay after the clocking
event.1
Don't know why VCS has such behavior, but with the flag "-ntb_opts no_cb_edge_override" the simulation runs as in Questa.
Related
I'm connecting a DDR model in the test bench using wires with net delay to model the trace delay on the board. The trace can hold 1 or 2 bits in its transmission line, but because the simulators models the net delay as inertial delay, all the bits get filtered out as glitches. I don't even get the clock this way. The SystemVerilog spec is not explicit on this subject. So, I'm guessing that the simulators don't want to incur the cost on performance and storage to model it as transport delay. However, I strongly believe transport delay is the right way to use for net delay, because otherwise the hassle of modeling each bidir signal with its own delay is huge. What do you think?
Here's my test case.
`timescale 1ps/1ps
module sim_top ();
parameter realtime NET_DELAY = 80ps;
parameter realtime PULSE_DELAY = 50ps;
logic driver;
initial begin
driver = 0;
forever #PULSE_DELAY driver = !driver;
end
wire #NET_DELAY a;
assign a = driver;
always #(posedge a or negedge a) begin
$display("a=%b # %t", a, $time);
end
logic b;
always #(*) begin
b <= #NET_DELAY driver;
end
always #(posedge b or negedge b) begin
$display("b=%b # %t", b, $time);
end
initial begin
#1ns;
$finish;
end
endmodule
Transport delay could be simulated by using #delays with non-blocking assighments:
always #*
out <= #delay input;
this is close to an inertial delay:
assign
#delay out = input;
The rest are mostly behavioral simulation artifacts which should be used in testbench only.
I had found this paper very informative for this issue:
http://www-inst.eecs.berkeley.edu/~cs152/fa06/handouts/CummingsHDLCON1999_BehavioralDelays_Rev1_1.pdf
So, I'm guessing that the simulators don't want to incur the cost on performance and storage to model it as transport delay.
I can imagine how you got that reasoning. From what I have learned, your assumptions is incorrect.
Real logic gates have inertial delay. This delay is caused by RC (resistance & capacitance) that is inherit to the device, from routing, or intentionally added. Verilog uses inertial delay to emulate delay behavior of real logic.
I cannot find a citation, but from discussions with engineers with pre-Verilog experience, early Verilog only modeled gates (think Verilog primitives and,or,nand,bufif0, etc.). Assign statements and always blocks were added some time later along with the possibility of synthesis. Non-blocking (<=) assignments were added much later (and copied from VHDL from what I've heard), but sill before Verilog by IEEE.
Assign statement handle delay the same way as gates. See IEEE1800-2012 § 10.3.3 Continuous assignment delays
A delay given to a continuous assignment shall specify the time duration between a right-hand operand value change and the assignment made to the left-hand side. If the left-hand references a scalar net, then the delay shall be treated in the same way as for gate delays; that is, different delays can be given for the output rising, falling, and changing to high impedance (see 28.16).
I'm guessing assign statements use the same type of delay as gates to reuse existing code (inside the simulator, not Verilog code) for managing delay and maintains continuity for the definition of delay. It also mapping easier, ex: assign #1 out = in; is the same as buf #1 (out,in);.
With real circuits, when you want a delay of 10 with a filter of 0.5, you need chain of 20 delay cells with small RC. If you want a delay and filter of 10 you use one delay cell with large RC. In theory synthesizers could use this delay information for target delay and filtration control (I cannot think of any synthesizer that actually does this; all synthesizers I know of ignore RTL delays).
Generally non-blocking (<=) assignments are used for synchronous logic (edge-sensitive flops and level-sensitive latches). Transport delay is the main exception but should only be used for behavioral modeling that will not be synthesized. If you know the amount of filtering your real delay path will have, I suggest coding it as follows:
reg out;
wire #(FILTER) in_filtered = in;
always #* out <= #(TOTAL_DELAY-FILTER) in_filter; // must be >=0.0
Which is cleaner and less CPU intensive then the pure inertial delay approach:
localparam LENGTH = TOTAL_DELAY/FILTER; // must be an integer >=2
wire out;
wire [LENGTH-2 : 0] delay_chain;
assign #(FILTER) {out,delay_chain} = {delay_chain,in};
Assume we have a D-flip-flop.
in RTL simulation (No t_hold and t_setup here), If its data input and clk changes at the same time, what the output should be ? The value before clk rise or the value after it ?
To make it even harder,
If a data_in and clock are connected to same wire. what should be the flop's output be ? zero all time ? or one all time ?
I tried the last case in ModelSim, and I get that the output is 1 all the time, while I expect it to be 0.
I expect that the flop in RTL-simulation should simulate the value before the clock edge.
When you use a simulation you will see results depend on how this case interpreted in the simulator what you use.
As you wrote in simulation t_setup = 0, it means that you don't need to keep signal in that level (what should be caught by flip flop) some time before rising (or falling) edge of clock signal, but can be applied exactly in the same time with the rising (or falling) edge of clock.
Because you see all time of the simulation '1' on the output of flip flop
This code is supposed to increment a counter (outputting to LEDs) when one button is pushed and decrement it when the other one is pushed. It works OK with decrementing but on incrementing it changes LEDs to random configuration instead.
module LED_COUNTER( CLK_50M, LED, Positive, Negative );
input wire CLK_50M;
input wire Positive;
input wire Negative;
output reg[7:0] LED;
always#( posedge Positive or posedge Negative )
begin
if(Positive == 1)
LED <= LED + 1;
else
LED <= LED - 1;
end
endmodule
I am using this board: http://www.ebay.com/itm/111621868286. The pin assignment is:
The connections:
After swapping pin assignments for buttons the behavior stays the same.
As others have already pointed out, you should be clocking with the CLK_50M and you should de-bounce your inputs (some FPGAs do it for you automatically, check your manual).
The reason you see partial functionality is from the way the synthesizer interprets the RTL. If the sensitivity list is edge triggered and that signal is referenced in the body of the always block, then the synthesizer will think it is an asynchronous level sensitive signal. This is intend for asynchronous reset & set (sometimes named clear & preset). ASIC design typically use flops with asynchronous reset in most the design. FPGAs tend to have a limited number of flops with asynchronous set or rest, so check your manual and use sparingly.
With your code, Negative is the clock and Positive is treated as an active high asynchronous input.
Modify the code to a functional behavioral equivalent (in simulation) seen below, then Positive will be the clock and Negative will be the active high asynchronous input.
always#( posedge Positive or posedge Negative )
begin
if(Negative == 1)
LED <= LED - 1;
else
LED <= LED + 1;
end
There are several resource for learning Verilog available online (use your favorite search engine), and I have some resources posted on my profile though more aimed at SystemVerilog.
Here is some pseudo code to point you in the correct direction for your project:
always #(posedge CLK_50M)
begin
past_Positive <= Positive;
// ...
case({/* ... , */ past_Positive,Positive})
4'b0001 : LED <= LED + 1;
4'b0100 : LED <= LED - 1;
// ...
endcase
end
First, update the design to a synchronous design where state only changes at rising edge of the CLK_50M, like
always#( posedge CLK_50M)
begin
...
end
Then add de-bounce logic logic for the two switch inputs; see contact bounce. This can be done with a small module you write yourself; that is a good exercise.
Output from the contact de-bounce logic can then be used for change detection, to make a single cycle indication each time a contact is pressed, and this indication can then be used to update the counter.
You have no debounce circuitry or logic. A mechanical switch will physically bounce a lot, so your 50MHz clock is going to see many, many transitions on the input signal, leading to erratic behavior.
I forgot to mention that you're not even using that 50MHz clock in a synchronous design. Rather you're asynchronously looking for transitions.
You need a low-pass filter somewhere. Either implemented with analog components on the input signal, or as a counter in hardware.
Let's take the example code below:
always #(posedge clock)
begin
if (reset == 1)
begin
something <= 0
end
end
Now let's say reset changes from 0 to 1 at the same time there's a posedge for the clock. Will something <= 0 at that point? Or will that happen the next time there's a posedge for the clock (assuming reset stays at 1)?
It depends on exactly how reset is driven.
If reset and something are both triggered off the same clock, then something will go to 0 one clock cycle after reset goes to 1. For example:
always #(posedge clock)
begin
if (somethingelse)
begin
reset <= 1;
end
end
If reset is synchronous and based on clock, The simulatore will defiantly see reset on the next clock and not the current. Physical design has clock-to-Q, therefor a rise in reset will not be observed in the same clock that caused it. You may see reset at the same time as clock in waveform. reset <= 1'b1; make the assignment happen near the end of the scheduler (after all code has executed).
To not have to worry about this when looking at a waveform, some logic designers like to put a delay on the assignment creating an artificial clock-to-Q delay (ex reset <= #1 1'b1; and something <=#1 0;). Synthesis tools will ignore the delay, but some will give warnings. That warning can be avoided by using a macro.
`ifdef SYNTHESIS
`define Q /* blank */
`else
`define Q #1
`endif
...
reset <= `Q 1'b1;
...
something <=`Q 1'b1;
...
If reset is asynchronous and being use with synchronous reset, setup time requirements need to be respected. In simulation if clock and reset rise at the same time, it is up to your verilog scheduler to decide if reset will be the new value or old value. Usually it will take the left-hand side value (old value), which means the reset will be missed on the current clock. Physical design uncertainly as well with a meta-stability risk.
The code you have written infers a flip-flop with synchronous reset. This means it is assumed that the "reset" signal is synchronised to the "clock" domain before being used in this way. If the "reset" signal is not synchronised then you should modify the code to infer a flip-flop with asynchronous reset as below:
always#(posedge clock or posedge reset)
begin
if (reset)
something <= 0
else
something <= something_else
end
Coming back to your question and assuming the code you have written is what you want, the outcome depends on how the reset is driven. If it is synchronous then the simulator will see it in the next clock edge. If it is asynchronous then the simulator can assume anything, it can vary from simulator to simulator. Please note that in simulator everything is a sequence of events and there is no such thing as happening at the same time.
In the physical world, what you have coded will result in a flip-flop with reset signal being one of the inputs to the combo driving the input of this flop. Now if the reset is synchronous, you are guaranteed that there will be no setup or hold violation at this flop. Whether the flop will 'see' the reset in this clock or the next depends on the various delays of the synthesised circuit (Usually this is the main reason that the reset is always held for few clock cycles to make sure all the flops in your design sees the reset). If reset is asynchronous then the flop will go into a metastable state. You will never want this in your design.
Hope this clarifies.
The short answer is that either of your two outcomes (immediately, or next cycle) could happen. This is a standard race condition, and simulators are free to handle this any way they want; some will give one answer, and others will give the other one.
For the long answer, look up any introductory text on how VHDL delta cycles work. Verilog doesn't specify 'delta cycles', but any Verilog simulator will work in exactly the same way, with some (irrelevant) changes in the overall scheduling algorithm. In this case, the scheduler finds that it has two events on the queue in a specific delta - reset rising, and clock rising. This is what "at the same time" means. It chooses one in an unspecified way (it might be earlier in the text source, or later, for example), works through all changes associated with that edge, and then goes back and works through all changes associated with the other edge.
i just want to know the difference between this two statement
always #(posedge CLK)
begin
state <= next_state;
end
AND:
always #(CLK)
begin
case(CLK)
1'b1:
state <= next_state;
1'b0:
state <= state;
end
Is there a difference between both ?
Thanks
Not quite. posedge detects these transitions (from the LRM):
Table 43—Detecting posedge and negedge
To 0 1 x z
From
0 No edge posedge posedge posedge
1 negedge No edge negedge negedge
x negedge posedge No edge No edge
z negedge posedge No edge No edge
So, 0->x is a posedge, for example. Your second example only detects cases where CLK ends up as 1, so misses 0->x and 0->z.
The IEEE Std. 1364.1(E):2002 (IEC 624142(E):2005), the Verilog register transfer level synthesis standard, states in Sec. 5.1 that an always block without any posedge/negedge events in the sensitivity list is combinational logic. I.e. the signals in the event list are ignored and the block is synthesized as if an implicit expression list (#(*), #*) was used. The following example is given in the standard ("Example 4" on page 14):
always # (in)
if (ena)
out = in;
else
out = 1’b1;
// Supported, but simulation mismatch might occur.
// To assure the simulation will match the synthesized logic, add ena
// to the event list so the event list reads: always # (in or ena)
(the comment is also copied from the standard document)
I.e. for a synthesis tool your second block is effectively:
always #*
begin
case(CLK)
1'b1:
state <= next_state;
1'b0:
state <= state;
end
which is just a multiplexer with CLK as select input, next_state as active-1 input and the output (state) fed back as active-0 input. A smart synthesis tool might detect that this is identical to a d-type latch with CLK as enable-input and create a d-type latch instead of a combinational loop. Note that the synthesis tool is not required to detect this latch because the code explicitly assigns state in all branches (compare Sec. 5.3. of the standard).
Either way this is different from the d-type flip-flop your first code example would synthesize to. This is one of many cases where Verilog-code has different meaning in simulation and synthesis. Therefore it is important to (1) write synthesizeable Verilog code in a way that avoids this cases and (2) always run post-synthesis simulations of your design (even if you are also using formal verification!) to make sure you have successfully avoided this pitfalls.
Functionally, those two circuits describe the same behavior in verilog, so I think there should be no difference.
However you should generally use the first style, as that is the one that is standard for writing synthesizable code, and most understandable by anyone else reading your code. The latter style, while describing the correct behavior, may confuse some synthesizers that don't expect to see clocks that are both sensitive to positive and negative edge.
The two blocks are VERY different.
The top one gives you a flip-flop while the bottom one gives you a latch with a multiplexer with the CLK as the select signal.
The critical difference between the two blocks is that the top one is a synchronous block i.e. the posedge clk part while the bottom one is asynchronous with the CLK level, not edge.
A verilog simulator could do left-hand sampling of CLK, effectively making the the case(CLK) version the same as a negedge CLK flop. Otherwise the simulator will treat it like a posedge CLK flop. It really depends how it is handled in the scheduler of specific simulator (or how a particular synthesizer will process it).
The most common codding styles all use the first condition. It is explicitly clear to the synthesizer and anyone reading the code that state is intended to be a flip-flop with a positive edge clocking trigger.
There is also a simulation performance differences. The posedge CLK performances 2 CPU operations every clock period, while the case(CLK) will perform 6 CPU operations every clock period. Granted in this example the differences is insignificance, but in large designs the poor coding used everywhere will add up to hours of simulation time wasted.