I want CODE 1 and CODE 2 to do the same
module testModule #( parameter LEN = 4,
parameter logic [0:0] OPTION = 1'b0 )
(
input Clk,
input [ 7:0][LEN-1:0] DataIn,
input [ 7:0][LEN-1:0] Factor,
output [15:0][LEN-1:0] DataOut_1,
output [15:0][LEN-1:0] DataOut_2
);
// CODE 1
always_ff #(posedge Clk) begin
for (int i = 0; i < LEN; i++) begin
if (OPTION == 1'b0) begin
DataOut_1[i] <= DataIn[i] * Factor[0];
end else begin
DataOut_1[i] <= DataIn[i] * Factor[i];
end
end
end
// CODE 2
always_ff #(posedge Clk) begin
for (int i = 0; i < LEN; i++) begin
int select = (OPTION == 1'b0) ? 0 : i;
DataOut_2[i] <= DataIn[i] * Factor[select];
end
end
endmodule
OPTION can be either 0 of 1.
But I get the following errors in CODE 2 in line
int select = (OPTION == 1'b0) ? 0 : i;
Local static variable with initializer requires 'static' keyword
automatic variable illegal in static variable initializer
I don't want to simplify the for loop because the in my original code I need it
This question is a variant on this other but I didn't want to change the original code question
You have a couple of issues there:
you cannot assign to a net inside an always block. DataOut_1/2 are declared as nets. So, you should declare them as regs at minimum:
output reg [15:0][LEN-1:0] DataOut_1,
output reg [15:0][LEN-1:0] DataOut_2
All variables defined in the module are static by nature. Except in some cases. The i defined in the 'for' loop is automatic. Therefore you cannot use it as an initializer to a static variable. You need to declare 'select' as automatic:
automatic int select = (OPTION == 1'b0) ? 0 : i;
Related
I am trying to get a code similar to this to work:
module testModule #( parameter LEN = 4,
parameter logic [0:0] OPTION = 1'b0 )
(
input Clk,
input [LEN-1:0] DataIn,
input [LEN-1:0] Condition,
output [LEN-1:0] DataOut_1,
output [LEN-1:0] DataOut_2
);
// CODE 1
always_ff #(posedge Clk) begin
for (int i = 0; i < LEN; i++) begin
if (OPTION == 1'b0) begin
if (Condition[0]) begin
DataOut_1[i] <= DataIn[i];
end else begin
DataOut_1[i] <= 1'b0;
end
end else begin
if (Condition[i]) begin
DataOut_1[i] <= DataIn[i];
end else begin
DataOut_1[i] <= 1'b0;
end
end
end
end
// CODE 2
always_ff #(posedge Clk) begin
for (int i = 0; i < LEN; i++) begin
int select = (OPTION == 1'b0) ? 0 : i;
if (Condition[select]) begin
DataOut_2[i] <= DataIn[i];
end else begin
DataOut_2[i] <= 1'b0;
end
end
end
endmodule
OPTION can be either 0 of 1.
I would like CODE 1 and 2 to do the same thing, and I am trying to simplify CODE 1.
DataOut_1 and DataOut_2 return the same value, but I get the following errors in CODE 2 in line
int select = (OPTION == 1'b0) ? 0 : i;
Local static variable with initializer requires 'static' keyword
automatic variable illegal in static variable initializer
And I am not sure if there is a way to do it
This code is illegal because you are not allowed to declare an implicitly static variable select with an initialization expression.
The reason for this restriction is exactly for the mistake you have made thinking that select will get initialized each time through the loop. Variables with static lifetimes only get initialized once at time zero, whereas variables with automatic lifetimes get initialized each time they enter the procedural block they are declared in.
Verilog declarations inside procedural block are implicitly static (exceptions are variables i declared as part of a for loop, and variables declared inside class methods, which are automatic.
There are a number of ways to fix this.
Explictly declare select with an automatic lifetime so that it gets initialized each iteration of the for loop.
Separate the declaration and initialization into a declaration and assignment statements. The assigment statement executes each iteration of the loop
Get rid of the variable and embed it onto the other expressions. That is essentially what code 1 and another answers does.
You can simplify CODE 1 by using a ternary and bitwise operator instead of the for loop:
module testModule #( parameter LEN = 4,
parameter logic [0:0] OPTION = 1'b0 )
(
input Clk,
input [LEN-1:0] DataIn,
input [LEN-1:0] Condition,
output reg [LEN-1:0] DataOut_1
);
always_ff #(posedge Clk) begin
if (OPTION == 1'b0) begin
DataOut_1 <= (Condition[0]) ? DataIn : '0;
end else begin
DataOut_1 <= DataIn & Condition;
end
end
endmodule
I am Writing a Verilog function to Locate the index of the first one on the right in the vector.If the vector has no ones, the function should returns the value to the vector’s highest index + 1. Here is the code :
module m ();
parameter n = 3;
function integer Locate_one (input [n-1:0] a );
Locate_one ='dx;
for (integer i =n-1 ; i<=0 ; i=i-1)
begin
if(a[i] == 1'b1)
begin
Locate_one=i;
break;
end
end
if (Locate_one=='dx)
Locate_one=n;
endfunction
initial begin
reg [n-1:0] a = 3'b111;
integer result = Locate_one (a);
$display("output is %d ", result);
end
endmodule
Th questions are as follows :
How to break out of the function when we find the highest one ? I have used the keyword break, which is as I found online, is a valid SystemVerilog keyword not Verilog Keyword.
The strategy that I have used to know that there is no one in the vector is that I have initialized the return integer to X and then I have compared the variable to X at the end of the function. Is this a good way to do so or there is another better way to do this comparison ?
There are a number of problems with your code.
You cannot use the == to compare with x—it always returns false. you must use the === operator
You are initializing two static variables a and result and the order of initializations is not defined. They are not procedural statements. SystemVerilog has made implicitly static variable initializations inside procedural code illegal, and that is the only backward incompatibility with Verilog I can think of.
Your code has a lot of SystemVerilog constructs besides break
declaring a variable in a for loop
a function/task body without begin/end keywords.
You should not be using x values in your code. It's not synthesizable, and it makes debugging your code more difficult if you made a mistake.
Your loop condition was the opposite of what you needed.
You can use a disable statement to get functionality similar to a break if you want strict Verilog compatibility.
module m ();
parameter n = 5;
function integer Locate_one (input [n-1:0] a );
integer i;
begin : block
Locate_one = n;
for (i =n-1 ; i>=0 ; i=i-1)
begin
if(a[i] == 1'b1)
begin
Locate_one=i;
disable block;
end
end
end
endfunction
reg [n-1:0] a = 3'b111;
initial begin
integer result;
result = Locate_one (a);
$display("output is %d ", result);
end
endmodule
Here is the SystemVerilog code
module m ();
parameter n = 5;
function int Locate_one (input [n-1:0] a );
Locate_one = n;
for (int i =n-1 ; i>=0 ; i=i-1)
begin
if(a[i] == 1'b1)
begin
Locate_one=i;
break;
end
end
endfunction
logic [n-1:0] a = 3'b111;
int result;
initial begin
result = Locate_one (a);
$display("output is %d ", result);
end
endmodule
I would go with a temp variable inside the function block, indicating if the "1" has been found. It wasn't necessary to initialise the index variable with X's, this should do the work: (I believe this is for simulation purposes as there are no input/output ports)
module first_one ();
parameter n = 3;
reg [n-1:0] a;
function integer locate_one;
input [n-1:0] a;
integer i;
reg found_temp;
begin
found_temp = 0;
for (i=0; i<n; i=i+1) begin
if(a[i] == 1'b1 & ~found_temp) begin
locate_one = i;
found_temp = 1;
end
end
if(~found_temp)
locate_one = n;
end
endfunction
initial begin
a = 0;
$monitor("a = %b : index = %d", a, result);
#100 $finish;
end
wire [$clog2(n)-1:0] result = locate_one(a);
always
#1 a = $urandom;
endmodule
This can be tested with icarus verilog:
iverilog first_one.v -o first_one.tb
vvp first_one.tb
I have a 32-bit input port pins and a 32-bit input enable pin_en, and want to generate a 16-bit output selected by the enables. I wrote verilog like this, but seems there are some errors.
How can I fix it or any other way to achive? Thanks!
ps: No more than 16 pins selected by en, but maybe less.
input [31:0] pins;
input [31:0] pin_en;
output [15:0] actual_pins;
generate
genvar i;
localparam cnt = 0;
for(i = 0; (i < 'd32) & (cnt < 'd16); i = i + 'd1) begin : b1
if(pin_en[i]) begin
assign actual_pins[i] = pins[cnt];
cnt = cnt + 'd1;
end
end
if(cnt < 16)
assign actual_pins[16 : cnt] = 'b0;
endgenerate
I think that there are several errors in you code:
in generate blocks you cannot do any generation, based on the actual values of variables. The blocks are for the constant expressions only which could be resolved at compilation time, not at the run time. Also, you cannot modify anything in the generated blocks besides genvars. Paremeters (localparams) cannot be modified, so the cnt = cnt + 1 is just illegal there.
you messed up actual_pins and pins. by logic there should be actual_pins[cnt];
you use binary & operator, but you should have used logical && instead.
So, all your code should have been implemented in a run-time constructs, i.e., always blocks. You also need a trigger which will cause the always block to be evaluated. I created a small example where the always block is to be triggered by a clock.
module top (
input clk,
input [31:0] pins,
input [31:0] pin_en,
output reg [15:0] actual_pins
);
always #(posedge clk) begin
int cnt = 0;
int i;
for(i = 0; (i < 'd32) && (cnt < 'd16); i = i + 'd1) begin
if(pin_en[i]) begin
actual_pins[cnt] = pins[i];
cnt = cnt + 'd1;
end
end
for(; cnt < 16; cnt = cnt + 1)
actual_pins[j] = 1'b0;
end
endmodule
Consider the following function which I would like to parameterize. I have created some parameters to set a width of the input and a corresponding width parameter for the output.
parameter SELECT_WIDTH = 6;
parameter PRIENC_WIDTH = $clog2(SELECT_WIDTH+1);
function [PRIENC_WIDTH-1:0] prienc6;
input [SELECT_WIDTH-1:0] select;
reg [PRIENC_WIDTH-1:0] out;
begin
casex(select)
6'b000001: out = 3'b101; // Is it possible to parameterize the case statement with generate
6'b00001x: out = 3'b100;
6'b0001xx: out = 3'b011;
6'b001xxx: out = 3'b010;
6'b01xxxx: out = 3'b001;
6'b1xxxxx: out = 3'b000;
endcase
prienc6 = out ;
end
end function
Obviously, the casex statement cases will not expand as written.
So I tried the following, which didn't compile correctly indicating unexpected generate found.
function [PRIENC_WIDTH-1:0] prienc_n;
input [SELECT_WIDTH-1:0] select;
reg [PRIENC_WIDTH-1:0] out;
begin
genvar gv_j;
casex(select)
for (gv_j = 0; gv_j < SELECT_WIDTH; gv_j = gv_j + 1)
begin
{{(SELECT_WIDTH-1)-gv_j{1'b0}},1'b1,{gv_j{1'bx}}} : out = (SELECT_WIDTH-1)-gv_j;
end
endcase
prienc_n = out ;
end
end function
I have been able to get the correct behavior using parameterized if's, but it seems like I should be able to parameterize that casex statement. Any thoughts on how to do this? I guess what I will try next is to wrap the casex in the generate loop and create 6 casex statements, each with only one state.
Since you tagged this question with SystemVerilog, I'll show you how to do this without a case statement or generate
function logic [PRIENC_WIDTH-1:0] prienc_n(
input [SELECT_WIDTH-1:0] select);
for (int j = 0; j < SELECT_WIDTH; j++) begin
if (select[SELECT_WIDTH-1]) return j;
select <<=1;
end
// if no 1 found
return ('x); // you did not specify this case
endfunction
If you need to stay in Verilog, it will need an intermediate variable
function reg [PRIENC_WIDTH-1:0] prienc_n(
input [SELECT_WIDTH-1:0] select);
reg [PRIENC_WIDTH-1:0] out;
integer j;
begin
out = {PRIENC_WIDTH{1'bx}}; // what should be returned if no 1 found
for (j = 0; j < SELECT_WIDTH; j = j + 1) begin
if (select[SELECT_WIDTH-1]) begin
out = j;
select = 0;
end
select = select << 1;
end
prienc_n = out;
end
endfunction
I have the Verilog code shown below, and if I try to compile it I get an error message. The point is that I'm trying to manipulate an input, which as long as I know cannot be done in Verilog. The point is that I need check the following condition in Verilog:
static int prime(unsigned long long n)
{
unsigned long long val = 1;
unsigned long long divisor = 5;
if (n == 2 || n == 3)
return 1;
if (n < 2 || n%2 == 0 || n%3 == 0)
return 0;
for ( ; divisor<=n/divisor; val++, divisor=6*val-1)
{
if (n%divisor == 0 || n%(divisor+2) == 0)
return 0;
}
return 1;
}
At the moment I have the following code:
module prime(clk, rst, start, A, ready, P);
input clk, rst, start;
input [7:0] A;
output ready, P;
reg ready, P;
wire [7:0] divisor;
assign divisor = 5;
wire [7:0] val;
assign val = 1;
always # (posedge clk or posedge rst) begin
if (!rst) begin
P <= 0;
end
else if (start) begin
case (A)
0 : P <= 1;
1 : P <= 1;
2 : P <= 1;
3 : P <= 1;
endcase
if (A%2 == 0 && A != 2) begin
P <= 0;
end
else begin
for( ; divisor <= A/divisor; val=val+1, divisor=6*val-1) begin
if (A%divisor == 0 || A%(divisor+2) == 0) begin
P <= 0;
end
end
// need to set P to 1
end
end
end
endmodule
Please also note I need to test primes in the form of 6n+1 or 6n-1, and I also need to assume in my code that 0 and 1 are also primes.
If I try the above code I get an error message saying:
Enhanced FOR loop is not enabled for verilog
If anyone can help me solve the error and finish my logic in Verilog, I would be glad.
The Verilog BNF does not allow empty or compound statements in for(;;). Change the file to *.sv to compile it under SystemVerilog rules. Otherwise change your for loop statement to have simple statements
for( divisor =5; divisor <= A/divisor; divisor=6*val-1) begin
if (A%divisor == 0 || A%(divisor+2) == 0) begin
P <= 0;
end
val++;
end
Also, you can't make procedural assignments to wires. make them variables.