Consider the following assignment
A1 = (b[3:0] ==c[3:0] & d[3:0]==e[3:0]) ? 1'b1 : 1'b0 ;
A2 = (b[3:0] ==c[3:0] && d[3:0]==e[3:0]) ? 1'b1 : 1'b0 ;
Are the 2 assignments equivalent or they could be different depending on tools?
Is it possible that (b[3:0] ==c[3:0]) evaluated as T/F is dependent on tool Whether it stores T as '1' or '0'.
The result of the equality, relational and logical operators are defined in sections 11.4.4-7 of the IEEE 1800-2017 LRM. There is no room for implementation differences. Truth is defined as 1'b1, and false is defined as 1'b0.
Note there are slight differences in precedence between the logical and bitwise operators, and it's easy to mix them up when you start dealing with multiple bit results, so use the bitwise operators only if your intent is to deal with multi-bit results.
Related
I have logic to compare a variable with multiple values.
For example:
logic [3:0] a;
always_comb begin
flag = (a == 'd13) || (a == 'd2) || (a=='d1); //can this be simplified?
end
Is there a easy way to write this statement?
This is more concise using the inside operator:
always_comb begin
flag = (a inside {1, 2, 13});
end
This is more scalable as well, allowing you to easily add or remove values from the set.
The syntax also supports ranges of values:
flag = (a inside {[1:2], 13});
Refer to IEEE Std 1800-2017, section 11.4.13 Set membership operator.
Since the values in the set are all constants, it should be synthesizable (but YMMV).
I am trying to understand some of the System Verilog syntax. I was struggling to finish an assignment and I came across this solution, but I do not understand why it works.
localparam int lo = w;
uwire [n:0] lo_bits, hi_bits;
assign answer = lo_bits == nlo ? lo_bits + hi_bits : lo_bits;
This is not exactly what I have in my code, but my question is the following: Why can't I rewrite this to a simple if-else block as such?
if (lo == lo_bits)
assign answer = lo_bits + hi_bits;
else
assign answer = lo_bits;
Verilog complains that lo_bits is a uwire and I cannot compare it with lo, but then why is it allowed in the example above? Aren't these two assignments equivalent?
Thank you very much for your help!
The difference is structural/declarative context versus procedural context. When you use an if clause in a declarative context (in this case it is at the same top level where you declare your wires and variables), it is considered a conditional generate construct (See Section 27.5 in the 1800-2017 LRM). This means the condition gets evaluated before simulation starts and must contain only constant expressions and no signals that can change during simulation. lo is a constant parameter, but not lo_bits.
If you want to use a procedural if, it needs to be inside a procedural block of code instantiated by always/initial blocks.
logic [n:0] answer;
always_comb
if (lo == lo_bits)
answer = lo_bits + hi_bits;
else
answer = lo_bits;
I have a line of code like
parameter [8:0] param1=8'd05, param2 = 8'd20;
A <= cond ? (1 << param1) : (1 << param2);
Will the compiler recognize 1 << param is a constant and replace that expression with a constant or will it try to implement some sort of bit shifter?
Parameters are evaluated at compile time and must be constants.
From IEEE Std 1364-2001:
3.11 Parameters Verilog HDL parameters do not belong to either the variable or the net group. Parameters are not variables, they are
constants.
So it is really up to the Synthesis tool how it will decide to implement a shift by that constant, but any reasonable implementation will simply select the correct wires out of the vector.
In addition, since your examples are constants shifted by a constant, the whole expression reduces to a constant and the code will be equivalent to:
A <= cond ? 32'h20 : 32'h100000;
I've seen Verilog code where the bitwise or operator ("|") is used monadic. What's the purpose?
For example
| address[15:14]==0
or
|address[15:14]? io_din : ramrd
Cann't we omit the "|" in these cases?
In this case it acts as a reduction operator, for example:
|4'b1000 => 1'b1 (OR)
&4'b1000 => 1'b0 (AND)
^4'b1000 => 1'b1 (XOR)
|4'b0000 => 1'b0
&4'b1111 => 1'b1
^4'b1111 => 1'b0
ORing the entire bus to a 1 bit value, or applying an AND/XOR to the entire bus.
This is referred to as a 'unary' operator as it only take a right hand argument. They are covered in Section 11.4.9 of SystemVerilog IEEE1800-2012.
|address[15:14]? io_din : ramrd
is the shortcut for writing
(address[15] | address[14]) ? io_din : ramrd
i.e bitwise ORing of all bits of the bus together to generate a 1bit value.
In this case it will evaluate as HIGH if either(or both) bit 15 OR bit 14 is HIGH.
similarly you can write other bitwise operators
&address[15:14]? io_din : ramrd // ANDing
^address[15:14]? io_din : ramrd // XORing
In the examples provided, the code with | is functionally equivalent to the same coded with the | omitted. Three possible reason to have and keep the | for the provided code are:
It gives guidance to the synthesizer: first OR the address bits then compare to 0, instead of comparing each address bit to 0 then ANDing the results. It is the same functional result with different gate configurations.
It following a coding style or formatting style requirement.
It just read better (visually/structurally appealing) because there is a |address[15:14]==1 on a near by line of code to |address[15:14]==0. (Reminder: |address[15:14]==1 is not the same as address[15:14]==1)
On the specific question of whether the '|' can be omitted in these cases:
Whether |address[15:14] and address[15:14] are identical depends on the context (in general, they aren't, because unknowns are handled differently). Your first example compared to 0, and it's true that the | can be dropped in this particular case, but it wouldn't be true if you compared to anything other than 0.
Your second example is trickier. The LRM doesn't appear to specify how the first expression in a ternary is evaluated. I know of 2 sims that evaluate it as a reduction-OR, so the | can be dropped in those cases. However, if a sim instead evaluates it in the same way as an if (ie if(address[15:14])) then the | is required.
Synthesis is simpler, of course, since the synthesiser doesn't have to worry about unknowns.
Say I have a scenario in which I need to compare only a few bits of a register and I don't care about other bits. eq, I need to check the first and last bits of a 3 bit register (A[2:0]) and I don't care about the middle bit, say compare vector is 3'b1X0 (Parameter).
Simplest way to do this is choose all the bits I care about, AND them and I have generated a control signal:
if ((A[2]==1) & ((A[0]==0)) Here the condition inside if statement is my control signal.
Another way is to use a casex statement: casex(A) begin 3'b1?0: ... , ... endcase.
Is there anything like ifx-elsex statement or something that can be used to do this kind of operation without using the 1st and 2nd method?
Thanks!
if (A[2:0] inside {3'b1?0} )
SystemVerilog keyword inside. It has been supported since at least Accellera's SystemVerilog 3.1 (before SystemVerilog was a part of IEEE). IEEE Std 1800-2012 11.4.13 has examples of use. inside is synthesizable.
There is also if ( A[2:0] ==? 3'b1?0 ) (IEEE Std 1800-2012 11.4.6). The only reference I have on hand (a book published 2004) says it is not supported for synthesis yet. You are welcome to try it.
(A[2]==1) is a logical expression the & is a bitwise operator, although either works it would be better semantics to use the && logical and operator. This is slightly different to most other languages where the && is a short-circuit operator.
Logically what you want is if ((A[2]==1) && ((A[0]==0)) but it could be reduced to a bitwise expression :
if ( ~A[0] & A[2] )
NB: Try to avoid using casex, the unknown parts will match x's in simulation. Try to use casez instead, ? can still be used to match don't cares.
Update comparing inside to casez
Case statements a clean control structure used in most languages to avoid large if elsif else chains. the inside operation will match x's to the do not care '?' values. this makes it usage similar to the casex which is considered to be bad practise to use as it can hide simulation fails.
casez(sel)
4'b1??? a= 3'd4;
4'b01?? a= 3'd3;
4'b001? a= 3'd2;
4'b0001 a= 3'd1;
4'b0000 a= 3'd0;
endcase
vs
if (sel inside {4'b1???})
a= 3'd4;
else if (sel inside {4'b01??})
a= 3'd3;
else if (sel inside {4'b001?})
a= 3'd2;
...
The above is actually equal to the casex (but more verbose) I believe that instead of casex you could also use :
case(sel) inside
4'b1??? a= 3'd4;
4'b01?? a= 3'd3;
4'b001? a= 3'd2;
4'b0001 a= 3'd1;
4'b0000 a= 3'd0;
endcase
but then I would never use a casex.
There's no operator I'm aware of that allows you to use '?' or 'x' inside an equality comparison to have them ignored.
Another alternative that you didn't mention would be to use a bitmask to select the bits you only care about. If you have a lot of bits this can be more compact than testing each bit individually.
If you only care about A == 3'b1?0, then it can be written as such:
if((A & 3'b101) == 3'b100)