In an example like this
function module(
input [3:0] in
output out);
for(integer i = in; i < in+10; i += 1) begin
// do stuff
end
endfunction
How would in be cast to i?
From what I understand an integer is a 32-bit bit vector, interpreted in 2's complement.
So does verilog pad the bit vector with 28{in[3]}?
From LRM
If needed, extend the size of the right-hand side, performing sign extension if, and only if, the type of the right-hand side is signed.
So, in your case i will be padded with '0', not with in[3], because in is not signed.
To do sign extension, you will need to make in signed: input signed [3:0] in;
Related
Imagine for simplicity that I have a 50-bit input into my module. This 50-bit input is split into ten 5-bit signed words. Is this how you would make each part of the input signed?
module(in, out)
input signed [49:0] in;
wire signed [4:0] in_temp [0:9];
genvar i;
for(i = 0; i < 128; i = i+1)
assign in_temp[i] = in[5*(i+1)-1 -: 5];
....
That's one way. You can also cast each slice using $signed(in[5*(i+1)-1 -: 5]), then you don't need an intermediate signal.
SystemVerilog adds another option. You can defined a packed array which is a 50-bit vector made up of 10 signed 5-bit vectors.
typedef logic signed [4:0] int5_t;
typedef int_5_t signed [9:0] int50_t;
module m(input int_50_t in, output out));
// can now use in[1] as a 5-bit signed signal which corresponds to bits [9:5] of the 50-bit vector
It does not matter if you make the result signed or unsigned. once you split up a wire it losses its meaning.
For example: If you split up signed 8'b00011111 into two equal parts you get 4'b0001 and 4'b1111. What would be the 'value' of each of those 4 bit numbers?
Only if you later concatenate them again in the right order do you get the original number back.
Answering you question:
It does not really matter but I would make all the individual parts unsigned as the top bit from all but one, is no longer a sign bit and as such the type can be confusing. You could be pedantic and make one signed and nine unsigned vectors.
What would be more useful is to use a name like in_split to indicate this is a part of a vector which has been split up.
If I reduce the number of bits after arithmetic right shift in verilog, do I still get the correct signed number? Is this valid?
number of bits reduced = shift value
A = 1110_1110
A>>>1
new A = 111_0111
Yes, but you should use three '>' not four and of course the new variable should be big enough:
wire signed [7:0] A,B;
wire signed [6:0] just_fits;
wire signed [5:0] oops;
assign B = A >>> 1; // Signed divide by two
assign just_fits = A >>> 1; // Signed divide by two
assign oops = A >>> 1; // Goes wrong
What I am trying to do in my mind is take 8 1-bit inputs and count the 1's. Then represent those 1's.
01010111 should output 0101 (There are five 1's from input)
module 8to4 (in,out,hold,clk,reset);
input [7:0] in; //1 bit inputs
reg [7:0] hold; //possible use for case statement
output [3:0] out; //Shows the count of bits
always #(clk)
begin
out = in[0] + in[1] + in[2] + in[3] + in[4] + in[5] + in[6] + in[7]; //Adds the inputs from testbench and outputs it
end
endmodule
Questions:
Is that the proper way to have 8 1-bit inputs? Or do I need to declare each variable as one bit ex: input A,B,C,D,E,F,G,H;
If my above code is close to being correct, is that the proper way to get out to display the count of 1's? Would I need a case statement?
I'm really new to verilog, so I don't even want to think about a test bench yet.
The way you wrote it is probably the better way of writing it because it makes it easier to parameterize the number of bits. But technically, you have one 8-bit input.
module 8to4 #(parameter WIDTH=8) (input [WIDTH-1:0] in,
output reg [3:0] out,hold,
input clk,reset);
reg [WIDTH-1:0] temp;
integer ii;
always #(clk)
begin
temp = 0;
for(ii=0; ii<WIDTH; i = i + 1)
temp = temp + in[ii];
out <= temp;
end
endmodule
Logically the code is proper.
However you can improve it like the following.
Make out as a reg, because you are using it in a procedural assignment.
Usage of reset. Ideally any code should have reset state, which is missing in your code.
Declare the direction (input/output) for hold, clk & reset port, which is currently not specified.
As dave mentioned, you can use parameters for your code.
I got the problem with using the input's value in Verilog.
I write:
module reg_vector (INPUT, ICLK, IENBL, NR, OUT);
parameter k = 6;
parameter n = 3;
input [(8*k)-1:0] INPUT;
input ICLK;
input IENBL;
input [n-1:0] NR;
reg [n-1:0] temp;
output reg [7:0] OUT;
always# (temp, posedge ICLK)
begin
if (IENBL)
begin
OUT = INPUT[temp*8 : temp*8+8];
end
end
endmodule
But got the error:
Error (10734): Verilog HDL error at reg_vector.v(25): temp is not a
constant
How should I fix it?
Thank you)
INPUT[temp*8 : temp*8+8] does not work because the : range syntax requires both sides to be a constant.
What you want is to use the +: array slicing: INPUT[temp*8 +: 8]
The left hand side of +: allows variables and represents the starting index. The right hand side is the width and must be a constant. For more on +: see Indexing vectors and arrays with +:
Other issues:
Remove temp from the sensitivity list.
temp needs to be assigned to something
OUT should be assigned with non-blocking (<=) not blocking (=) since it is sequential logic.
always #(posedge ICLK) // no temp in sensitivity list
begin
if (IENBL)
begin
OUT <= INPUT[temp*8 +: 8]; // non-blocking and +:
end
end
Even if your vector is always 1 byte wide, the tool understands it as a variable size and it does not know how to deal with it. (you also inverted the indexes temp*8 and temp*8+8 in the vector selection)
Another way to do it is to use the shift operator
OUT = INPUT >> (temp*8);
This should work as OUT will take the lower 8bits of the shifting by 8*temp of INPUT
I'm new to Verilog.
I have written code to convert a wire value to an integer:
wire [31:0] w1;
integer k;
always # (w1) k = w1;
Source: converting a wire value to an integer in verilog
Now, for the next part I get an ERROR!
wire [63:0] w2; // Suppose it contains some value
wire [63:0] w3;
assign w3[k-1:0] = w2[k-1:0]; // ERROR in this line
ERROR : k is not a constant.
How do I solve this issue?
Verilog requires that part selects (code like [msb:lsb] to select part of a vector) be constant. To access a variable-sized group of bits requires something more complicated. Here is one way to do it:
wire [63:0] src;
wire [6:0] k;
wire [127:0] mask = { { 64 { 1'b0 } }, { 64 { 1'b1 } } } << k;
wire [63:0] dest;
assign dest = mask[127:64] & src;
The technique here is to construct a vector of 64 zeros followed by 64 ones, shift that vector by a variable amount, and then use a portion of the vector as a qualifying mask to control which bits are transferred from src to dest.
A related concept which does not help in your example but which is worth being aware of: Verilog-2001 introduced the "indexed part-select". An indexed part select specifies a base index and a width. The width is required to be constant but the base index does not need to be constant. The syntax for an indexed part select is vec[base+:width] or vec[base-:width].
The part select operators in Verilog 2001 could be useful for what you want to achieve.
Basically verilog allows for the starting index to be variable but needs the width of the assignment to be constant. The "+:" operator indicates counting upwards from the index value and vice-versa for "-:".
You can do something like,
assign w3[k-1 -: 8 ] = w2[k-1 -: 8]; // Where 8 bits is copied downwards
Search for "+:" in the below document.
http://www.sutherland-hdl.com/papers/2001-Wescon-tutorial_using_Verilog-2001_part1.pdf
Word of caution, generally variable part selects is considered as bad verilog.