I have constructed a Pulse width modulating circuit that should output an amplitude of 10 Volts PWM signal. The control input signal is a 5Vpp, 100Hz sine wave and a pulse input of 10Vpp, 1kHz square wave.
I know that the VCC value controls the amplitude of the PWM output signal. However, I tried setting it to 10 volts and the oscilloscope did not display any signal. The only time the oscilloscope displays an output is when the VCC is set to 6.5 volts and below. The red signal is the PWM signal, the blue square wave is the pulse input and the green signal is the control signal.
Any thoughts as to why my circuit does not output an amplitude of 10V PWM signal? Please help me solve this problem.
You should post this question here- https://electronics.stackexchange.com/ Stackoverflow doesn’t deal with electronics related questions.
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I'm trying to understand how to implement audio playback from scratch on attiny85. The goal is to play a short sound (cat meows, so i want it to remain recognizable) from an array representing strength of audio signal sampled at fixed interval.
As far as i understand, signal strength is linearly mapped to voltage of analogue audio signal. As far as I know, audio cards are Digital to Analogue Converters, but attiny85 probably doesn't have that.
I'm curious if I can use pwm to play the sound back. Since pwm changes average voltage by changing duty cycle of alternating high and low phases of signal, it most likely would result in the drop of audio quality. Wav sampling rates can differ between 1 HZ and 4.3 GHz according to google. Attiny85 has internal clock with frequency up to 8MHz (which I hope is same for it's pwm generator).
Considering reconfiguring the timer and pwm settings as well as looping in the array, what is the maximum sampling rate of audio i can reliably play? And should i even try to do it with pwm, or there are better options?
Given a system clock of 8 MHz, you can use PWM to generate mono (single-channel) audio.
Consider a PWM period of 1000 clocks, giving you about 10 bit resolution. The sample rate will be 8000 Hz then, which gives you some kind of lo-fi audio.
If you reduce your signal resolution to 8 bits, you'll get 8 MHz / 28 = 31.25 kHz sample rate. This gets near hi-fi.
Synchronize your sample output with the PWM generator, and use an appropriate analogue filter.
Many years ago I built a digital door bell with a sample rate of 8 kHz and 8 bit samples. It played nice sounds in the quality of telephones. The microcontroller was a 8051 derivative and it used an R-2R ladder as DAC.
A simpel sinus can be generated by using a 50% PWM signal and varying the frequency. Given some filtering effect through the speaker, it would mimik a single tone audio signal.
Making more advanced tones (needed for natural sound) quickly gets more complicated and the duty cycle of the signal can also be used to trick the human ear into hearing harmonics. Check out the arduino function tone() for some inspiration.
Be carefull when connecting a small speaker to the Arduino, preferably a transistor/buffer/small amplifyer should be place between the Arduino and the speaker.
My simplified Simulink model involves plotting a sine wave going through an enabled subsystem. The simulation time step is 1/(125e6) seconds and the subsystem is only enabled once every 1/(250e3) seconds using a pulse generator. When the subsystem is disabled then the input sine data is 'lost' which is why the output looks like a jagged sine wave in the picture.
I need a way to pause the input data from flowing when the subsystem is disabled so that no sine data is 'lost'. The result should look like a very spread out sine wave. A simple way to accomplish this is to make the sine wave output at a frequency of 250kHz so that it's perfectly synced with the enabled subsystem, but this is not possible for my application.
I need to use an upsample block that has an upsample factor = 125e6/250e3 = 500. This will pad out my sample with an exact amount of 0's so that no data is missed when the enable block is disabled.
The stick has a 12MHz oscillator on board. http://www.latticesemi.com/icestick
I have managed to write verilog code to divide this clock down and flash LEDs are 1Hz. (I am just starting to learn verilog.)
I believe that this FPGA will work at up to 133MHz.
Is there a way to generate a faster clock signal (in verilog) from the 12MHz oscillator?
Answer not yet tested.
Via https://www.reddit.com/r/yosys/comments/3yrq6d/are_plls_supported_on_the_icestick_hw/
From: https://github.com/SubProto/icestick-vga-test/blob/master/vga.v
wire clk;
SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(4'b0001),
.DIVF(7'b1000010),
.DIVQ(3'b100),
.FILTER_RANGE(3'b001),
) uut (
.REFERENCECLK(pclk),
.PLLOUTCORE(clk),
.LOCK(D5),
.RESETB(1'b1),
.BYPASS(1'b0)
);
Also:
iCE40 sysCLOCK PLL
The iCE40 Phase Locked Loop (PLL) provides a variety of user-synthesizable clock frequencies, along with cus-
tom phase delays.The PLL in the iCE40 device can be configured and utilized with the help of software macros or
the PLL Module Generator. The PLL Module Generator utility helps users to quickly configure the desired settings
with the help of a GUI and generate Verilog code which configures the PLL macros. Figure 2 shows the iCE40 sys-
CLOCK PLL block diagram.
http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/IK/iCE40sysCLOCKPLLDesignandUsageGuide.pdf?document_id=47778
I have used a higher clock frequency to display a pong game in a VGA monitor using TinyFPGA BX. The TinyFPGA BX and the Lattice iCEstick are quite similar. Therefore, I would like to share my code. You may need to use the official Lattice software for an easier GUI (Graphical User Interface) configuration. https://www.latticesemi.com/software
module top(
input wire clk_16,
output USBPU
);
assign USBPU = 0; // drive USB pull-up resistor to '0' to disable USB
output wire;
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0110001), // DIVF = 49
.DIVQ(3'b101), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) uut (
.LOCK(locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clk_16), // clk_16_MHz is the original clock
.PLLOUTCORE(clk) // clk is the modified clock with higher frequency
);
I am using the Spartan 3e Xilinx FPGA board, and I am trying to sync two FPGAs to generate the same sine wave. Due to limited I/O pins there is only one connection from the Master to Slave. Is there a way to sync them up and set the phase of the sine wave?
For example when the master hits zero phase a flag raises and the slave is set to zero phase too.
The function prototype of the sine lut is given below. I am just starting out so any help is appreciated thank you.
sine sine_lut (
.ce(clock_enable), // input ce
.clk(CLK_50MHZ&& clock_enable), // input clk
.sclr(!clock_enable),
.pinc_in(line_freq[31:0]), // input [31 : 0] pinc_in
.poff_in(0), // input [31 : 0] poff_in
.sine(sine_generate[12:0]), // output [12 : 0] sine
.phase_out(phase_out) // output [31 : 0] phase_out
);
The method mentioned in the question would work to some extent:
If the jitter of the clocks is not that big to cause a significant desynchronisation during the period of the sine wave
If some discontinuity in the slave output is tolerable.
In order to overcome the discontinuity you can modify the method as following. Instead of just resetting the waveform, simply readjust the frequency of the signal on the slave to be slightly higher or lower for the next period, depending on whether it is too fast or too slow. You can do this using PID control technique, for example (the adjustment will be proportional to the phase error). Or simply recalculate the frequency based on the measured time between sync pulses.
If the sine wave frequencies are much slower than the clock frequency, you can utilise the PWM technique to encode the sine values of the master as a signal Duty Cycle, measure it on the slave and output the same value. A very small phase shift is expected, but again, it shouldn't be noticeable if the clock is much faster than the sine.
My objective is to have a verilog module with an input (from a DE2 board like a clock or key) that triggers an audio file to play. How can I accomplish this using Quartus and a DE2 board?
Just start with a blinking LED.
As second you can try a running light.
Lesson tree is start to make noise with your FPGA.
And now you can start to send samples from a memory to your speaker.
Don't forget: Simulate first, synthesize second!