Verilog testbench error multiplex 4x1 using EDAPlayground - verilog

Question

I'm doing a Multiplex 4x1 in Verilog using EDAPlayground, but I still get testbench errors, and I don't know why.
Here is one error:
ERROR VCP2000 "Syntax error. Unexpected token: and[_AND]." "design.sv"
26 6
module mux4x1(
input x1, x2, x3, x4, s0, s1,
output f);
wire s0_inv, out_x1, out_x2;
wire s1_inv, out_x3, out_x4;
wire out_mux1, out_mux2;
wire out_mux3, out_mux4;
// mux2x1_1
not (s1_inv, s1);
and (out_x1, s1_inv, x1);
and (out_x2, s1, x2);
or (out_mux1, out_x1, out_x2);
// mux2x1_2
not (s1_inv, s1);
and (out_x3, s1_inv, x3);
and (out_x4, s1, x4);
or (out_mux2, out_x3, out_x4);
// mux4x1
not (s0_inv, s0)
and (out_mux3, s0_inv, out_mux1);
and (out_mux4, s0_inv, out_mux2);
or (f, out_mux3, out_mux4);
endmodule
Link: https://www.edaplayground.com/x/bkNc

Answer 1

When I try to compile just your design code, I get this error:
and (out_mux3, s0_inv, out_mux1);
|
xmvlog: *E,EXPSMC : expecting a semicolon (';') [7.1(IEEE)].
Often this type of error is caused by the line of code above the reported line:
not (s0_inv, s0)
Just add the semicolon:
not (s0_inv, s0);
EDAplayground offers several different simulators, and some provide more helpful error messages than others. You have it set for Aldec; switch to Cadence, for example, to see a different error message.