verilog AND gate when 32 not working correctly - verilog

Question

The AND gate
module andgate
#(parameter Port_Num = 2,
parameter WIDTH=8)
(
input [(WIDTH-1):0] a,
input [(WIDTH-1):0] b,
input [(WIDTH-1):0] c,
input [(WIDTH-1):0] d,
input [(WIDTH-1):0] e,
input [(WIDTH-1):0] f,
input [(WIDTH-1):0] g,
input [(WIDTH-1):0] h,
output [(WIDTH-1):0] q
);
assign q = (a & b & c & d & e & f & g & h);
endmodule
The angate_sim
`timescale 1ns / 1ps
module andgate_sim();
// input
reg a=0;
reg b=0;
reg c=1;
reg d=1;
reg e=1;
reg f=1;
reg g=1;
reg h=1;
//outbut
wire q;
andgate #(8,1) u(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.q(q));
always #100 a=~a;
initial begin
#100 a=1;
#100 begin a=0;b=1;end
#100 a=1;
#60000000 $finish;
end
initial
begin
$dumpfile("wave2.vcd");
$dumpvars(0, andgate_sim);
end
endmodule
When I test the testbench, it worked correctly like this
iverilog -o Ex2 andgate.v andgate_sim.v
vvp -n Ex2 -lxt2
gtkwave wave2.vcd
The successful wave in wave2.vcd
Then I tried to make a AND gate*32 just like this
`timescale 1ns / 1ps
module andgate32_sim( );
// input
reg [31:0] a=32'h00000000;
reg [31:0] b=32'h00000000;
reg [31:0] c=32'hffffffff;
reg [31:0] d=32'hffffffff;
reg [31:0] e=32'hffffffff;
reg [31:0] f=32'hffffffff;
reg [31:0] g=32'hffffffff;
reg [31:0] h=32'hffffffff;
//outbut
wire [31:0] q;
andgate #(8,32) u(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.q(q));
always #100
begin
a <= 32'hffffffff;
end
always #200
begin
a <= 32'h00000000;
b <= 32'hffffffff;
end
always #300
begin
a <= 32'h007fa509;
end
always #400
begin
a <= 32'hffffffff;
end
initial begin
#100 a <= 32'hffffffff;
#100 begin a <= 32'h00000000;b <= 32'hffffffff;end
#100 a <= 32'h007fa509;
#100 a <= 32'hffffffff;
#60000000 $finish;
end
initial
begin
$dumpfile("wave2-2.vcd");
$dumpvars(0, andgate32_sim);
end
endmodule
But when I did the steps like before
iverilog -o Ex2 andgate.v andgate32_sim.v
vvp -n Ex22 -lxt2
gtkwave wave2-2.vcd
There was nothing in the wave like this
No waves in the wave2-2.vcd
Actaully, it should be something in the wave2-2.vcd.
Could you please help me ?

Answer 1

You are trying to run another compiled testbench "Ex22" instead of "Ex2".
Hint: You can use parameters and pass them to the instantiation, as:
localparam WIDTH = 32;
localparam Port_Num = 8;
// input
reg [WIDTH-1:0] a=32'h00000000;
reg [WIDTH-1:0] b=32'h00000000;
reg [WIDTH-1:0] c=32'hffffffff;
reg [WIDTH-1:0] d=32'hffffffff;
reg [WIDTH-1:0] e=32'hffffffff;
reg [WIDTH-1:0] f=32'hffffffff;
reg [WIDTH-1:0] g=32'hffffffff;
reg [WIDTH-1:0] h=32'hffffffff;
//outbut
wire [WIDTH-1:0] q;
andgate #(.Port_Num (Port_Num), .WIDTH (WIDTH)) u(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.q(q));