I wrote code in Verilog that is supposed to create a 12Hz square signal at 50MHz clock signal.
Is it correct?
module w_m(clk, cnt);
input clk;
output [21:0] cnt;
reg [21:0] cnt = 0;
always #(posedge clk)
cnt = cnt + 1;
endmodule
module w_tf;
reg clk;
wire [21:0] cnt;
w_m uut
(
.clk(clk),
.cnt(cnt)
);
initial begin
// Initialize Inputs
clk = 0;
forever begin
#10
clk = !clk;
end
end
endmodule
Yes, it correctly simulates as described, assuming the timescale is set to 1ns.
The clk period is 20ns, and its frequency is 50MHz.
The MSB of cnt (cnt[21]) has a frequency of approximately 12Hz (11.921Hz, according to my simulation results).
You can verifiy this by running a simulation and looking at waveforms. You can post your code on edaplayground, for example.
The logic is right. However, there are some inaccuracies. I have varied the register size in order to run the simulation as allowed by EDA playground.
DUT:
module w_m(clk, clk_out);
input clk;
//output [21:0] cnt;
output clk_out;
reg [11:0] cnt = 0; // make 11 to 21
always #(posedge clk)
cnt = cnt + 1;
assign clk_out = cnt[11];
endmodule
Also, the testbench needs a $finish to stop the forever block from running infinite, taking up the disk space. Added a parallel path in order to run the sim, and exit after 10000ns. You can vary this as per your need.
TB:
module w_tf;
reg clk;
wire cnt;
w_m uut
(
.clk(clk),
.clk_out(cnt)
);
initial begin
// Initialize Inputs
clk = 0;
fork
begin
forever begin
#10 clk = !clk; end
end
begin
#10000000 $finish; // increase this number as per the simulation requirement
end
join
end
endmodule
Related
I am trying to delay a 32-bit signal using shift register. My logic is a single flip flop delay a signal by 1 clk so I use shift register as it is combination of flip flop can someone guide me what is wrong with this code.
module delay_n_cycles (
input wire [31:0] data_in,
input wire clk,
output reg [31:0] data_out,
parameter N = 5
);
reg [31:0] shift_reg;
always #(posedge clk) begin
shift_reg <= {shift_reg[30:0], data_in};
if (N == 0) begin
data_out <= shift_reg[31];
end else begin
data_out <= shift_reg[N-1];
end
end
endmodule
First of all, your code is syntactically wrong. parameter cannot be declared in a way you provided.
Your shift register is only 32 bit wide. Usually, to delay multi-bit data this way, you need to keep N copies of data in the register, shift them at one end and read at the other. I guess the following should help:
module delay_n_cycles #(parameter N = 5)(
input wire [31:0] data_in,
input wire clk,
output reg [31:0] data_out
);
reg [N-1:0][31:0] shift_reg;
always #(posedge clk) begin
shift_reg <= (shift_reg << 32) | data_in;
data_out <= shift_reg[N-1];
end
endmodule
This code will work with system verilog because it used packed multi-dimensional arrays.
You need to shift the reg by 32 (width of the data) in packed version.
Here is an example of a testbench:
module tb();
bit clk;
int clkCount;
initial
forever begin
#5 clk = ~clk;
clkCount++;
end
logic [31:0] data_in, data_out;
initial begin
$monitor("%0t (%0d) [%h]: %0d --> %0d", $time, clkCount, ds.shift_reg[4], data_in, ds.data_out);
for(int i = 0; i < 20; i++) begin
#10 data_in = i;
end
$finish;
end
delay_n_cycles ds(data_in, clk, data_out);
endmodule
I am not getting any response from the uut in the testbench. The module exp2_up_down_counter works ok without testbench, but gives output as xxxx when instantiated in the testbench.
Here is the main module of the up-down counter:
`timescale 1ns/1ps
module exp2_up_down_counter (input clk, reset, mode, output reg [3:0] count);
always #(posedge clk)
if (reset == 1)
count <= 0; // reset the counter if reset is high
else if (mode == 1)
count <= count + 1; // works as up counter if mode pin is high
else
count <= count - 1; // works as down counter if mode pin is low
endmodule
Simulation without testbench:
Testbench for up-down counter
`timescale 1ns/1ps
module exp2_up_down_counter_tb;
reg clk, reset, mode;
wire [3:0] count;
exp2_up_down_counter uut(.clk(clk), .reset(reset), .mode(mode), .count(count));
initial begin
clk = 1'b0;
end
always #(*) #5 clk <= ~clk;
initial begin
// initializing the inputs
reset = 1;
mode = 0;
#5;
reset = 0;
#10
mode = 1;
#5000 $finish;
end
endmodule
Simulation with testbench:
In exp2_up_down_counter, count is declared as a reg. This means that its default value is X at time 0. Since the reset signal is synchronous to the clock, you need to wait for the 1st posedge of clock before you release the reset. Currently, the reset is released at the 1st posedge of clock in the testbench, which is a race condition. Therefore, count does not get assigned the value of 0, and it retains the value of X for the whole simulation.
You need to delay the reset release. For example, change:
#5;
reset = 0;
to:
#15;
reset = 0;
However, it is better to drive your synchronous inputs in the testbench the same way you drive your signals in the design: using #(posedge clk) and using nonblocking assignments (<=):
initial begin
reset = 1;
mode = 0;
repeat (2) #(posedge clk);
reset <= 0;
repeat (1) #(posedge clk);
mode <= 1;
#5000 $finish;
end
Also, this is a more standard way to drive the clock in the testbench:
always #5 clk = ~clk;
I'm trying to declare a simple clock wiggle task in a testbench, but ModelSim is claiming that no design element of my task's type exists. What's the problem with this code:
`timescale 1 ns/1 ns
module at25320a_tester();
reg clk, s_in, s_out, chip_select, write_protect, hold;
// Instantiate at25320a module
at25320a EEPROM (.SCK(clk), .SI(s_in), .CSNeg(chip_select), .HOLDNeg(hold), .WPNeg(write_protect), .SO(s_out));
run_clk(15);
task run_clk;
input [3:0] cycles;
output reg clk;
integer i;
for (i=0;i<cycles;i=i+1) begin
#100 clk = 1;
#100 clk = 0;
end
endtask
endmodule
Tasks must be called from a procedural block, such as always or initial. In your case, youll want to run the task in an initial block with a few modifications:
`timescale 1 ns/1 ns
module at25320a_tester();
reg clk, s_in, s_out, chip_select, write_protect, hold;
// Instantiate at25320a module
at25320a EEPROM (.SCK(clk), .SI(s_in), .CSNeg(chip_select), .HOLDNeg(hold), .WPNeg(write_protect), .SO(s_out));
initial begin
run_clk(15);
end
task run_clk;
input integer cycles; // Might as well not have this be bigger
// No clock, you want to use the clock from the module
integer i;
for (i=0;i<cycles;i=i+1) begin
#100 clk = 1;
#100 clk = 0;
end
endtask
endmodule
I'm new to verilog development and am having trouble seeing where I'm going wrong on a relatively simple counter and trigger output type design.
Here's the verilog code
Note the code returns the same result whether or not the reg is declared on the output_signal without the internal_output_buffer
`timescale 1ns / 1ps
module testcounter(
input wire clk,
input wire resetn,
input wire [31:0] num_to_count,
output reg [7:0] output_signal
);
reg [31:0] counter;
initial begin
output_signal = 0;
end
always#(negedge resetn) begin
counter = 0;
end
always#(posedge clk) begin
if (counter == num_to_count) begin
counter = 0;
if (output_signal == 0) begin
output_signal = 8'hff;
end
else begin
output_signal = 8'h00;
end
end
else begin
counter = counter + 1;
end
end
assign output_signal = internal_output_buffer;
endmodule
And the code is tested by
`timescale 1ns / 1ps
module testcounter_testbench(
);
reg clk;
reg resetn;
reg [31:0] num_to_count;
wire [7:0] output_signal;
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin
num_to_count = 20;
end
initial begin
#7 resetn = 1;
#35 resetn = 0;
end
testcounter A1(.clk(clk),.resetn(resetn),.num_to_count(num_to_count),.output_signal(output_signal));
endmodule
Behavioral simulation looks as I expected
But the timing simulation explodes
And for good measure: the actual probed execution blows up and looks like
Any tips would be appreciated. Thanks all.
The difference between the timing and functional simulations is that a timing simulation models the actual delay of logic gates while the functional simulation just checks if values are correct.
For e.g. if you have a simple combinational adder with two inputs a and b, and output c. A functional simulation will tell you that c=a+b. and c will change in the exact microsecond that a or b changes.
However, a timing simulation for the same circuit will only show you the result (a+b) on c after some time t, where t is the delay of the adder.
What is your platform? If you are using an FPGA it is very difficult to hit 500 MHz. Your clock statement:
forever #1 clk = ~clk;
shows that you toggle the clock every 1ns, meaning that your period is 2ns and your frequency is 500MHz.
The combinational delay through FPGA resources such as lookup tables, multiplexers and wire segments is probably more than 2ns. So your circuit violates timing constraints and gives wrong behaviour.
The first thing I would try is to use a much lower clock frequency, for example 100 MHz and test the circuit again. I expect it to produce the correct results.
forever #5 clk = ~clk;
Then to know the maximum safe frequency you can run at, look at your compilation reports in your design tools by running timing analysis. It is available in any FPGA CAD tool.
Your code seems working fine using Xilinx Vivado 14.2 but there is only one error which is the following line
assign output_signal = internal_output_buffer;
You can't assign registers by using "assign" and also "internal_output_buffer" is not defined.
I also personally recommend to set all registers to some values at initial. Your variables "resetn" and "counter" are not assigned initially. Basicly change your code like this for example
reg [31:0] counter = 32'b0;
Here is my result with your code:
Your verilog code in the testcounter looks broken: (a) you're having multiple drivers, and (b) like #StrayPointer notices, you're using blocking assignments for assigning Register (Flip-Flop) values.
I'm guessing your intent was the following, which could fix a lot of simulation mismatches:
module testcounter
(
input wire clk,
input wire resetn,
input wire [31:0] num_to_count,
output reg [7:0] output_signal
);
reg [31:0] counter;
always#(posedge clk or negedge resetn) begin
if (!resetn) begin
counter <= 0;
end else begin
if (counter == num_to_count) begin
counter <= 0;
end else begin
counter <= counter + 1;
end
end
end
assign output_signal = (counter == num_to_count) ? 8'hff : 8'h00;
endmodule
Our assignment is to build a rudimentary single-cycle CPU in Verilog, but I'm not getting even more fundamental modules of it correct. For instance, to test the Instruction Memory module, we've been given a text file "hw3Test.txt" with instructions in hex, and I'm trying to slurp that into the IM.
00221820
AC010000
8C240000
10210001
00001820
00411822
When I run a testbench, I see that the only instructions that get into memory are the second, third, and fourth lines. Here's the IM module:
module IM(addr, clk, inst);
input [31:0] addr;
input clk;
output reg [31:0] inst;
reg [31:0] mem [255:0];
initial begin
$readmemh("hw3Test.txt", mem);
end
always #( posedge clk) begin
inst=mem[addr[31:2]];
end
endmodule
And the testbench:
module imtest;
// Inputs
reg [31:0] addr;
reg clk;
// Outputs
wire [31:0] inst;
// Instantiate the Unit Under Test (UUT)
IM uut (
.addr(addr),
.clk(clk),
.inst(inst)
);
initial begin
// Initialize Inputs
addr = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
clk = 0;
addr = 0;
#100;
forever begin
#20;
clk = ~clk;
addr = addr + 4;
end
end
endmodule
I'm also not sure I'm even getting the PC-to-IM module correct, because aside from the initialized values, everything but the rst and clk signals show no valid values. Can anyone point out where I'm going wrong?
module pc_im(
// Inputs
rst, clk, PCin,
// Outputs
inst, PCout
);
input clk, rst;
input [31:0] PCin;
output reg [31:0] inst;
output reg [31:0] PCout;
PC mypc (
.clk(clk),
.rst(rst),
.PCin(PCin),
.PCout(PCout)
);
IM myim(
.clk(clk),
.addr(PCout),
.inst(inst)
);
endmodule
Here's the PC.v module:
module PC(rst, clk, PCin, PCout);
input clk, rst;
input [31:0] PCin;
output reg [31:0] PCout;
always #(posedge clk) begin
if (rst) PCout <= 0;
else PCout <= PCin + 4;
end
endmodule
And finally, the testbench:
module pcimtest;
// Inputs
reg rst;
reg clk;
reg [31:0] PCin;
// Outputs
wire [31:0] inst;
wire [31:0] PCout;
// Instantiate the Unit Under Test (UUT)
pc_im uut (
.rst(rst),
.clk(clk),
.PCin(PCin),
// Outputs
.inst(inst),
.PCout(PCout)
);
initial begin
// Initialize Inputs
rst = 1;
clk = 0;
PCin = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
forever begin
#100;
clk <= ~clk;
PCin <= PCout;
end
// Add stimulus here
end
endmodule
Here are a few things that look suspect.
Problem 1
It is normally good to use non-blocking assignments in blocks intended to infer registers.
i.e. change
always #( posedge clk) begin
inst=mem[addr[31:2]];
end
to
always #( posedge clk) begin
inst<=mem[addr[31:2]];
end
Problem 2
You are changing signals twice per clock cycle, once on negative edge and once on positive edge.
Change:
forever begin
#20;
clk = ~clk;
addr = addr + 4;
end
to
forever begin
#20;
clk = 1;
#20;
clk = 0;
addr = addr + 4;
end
Problem 3
You are using synchronous resets but not supplying a clock during reset.
Consider the code
always #(posedge clk) begin
if (rst) PCout <= 0;
else PCout <= PCin + 4;
end
This block will only activate on positive clock edges. However, you make reset high while the clock is paused so no reset will happen.
Change
rst = 1;
clk = 0;
PCin = 0;
// Wait 100 ns for global reset to finish
#100;
to
rst = 1;
clk = 0;
PCin = 0;
#20
clk = 1;
#20
clk = 0;
// Wait 100 ns for global reset to finish
#100;