why does my output signal have 2 clock cycles delay? - verilog

Question

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).
Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the 'reset' event occurs one cycle earlier than the 'set' event, so there is no conflict here.
In the example waveform below, reset, in1 and out1 are shown again separately for clarity.
my code:
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out );
integer i;
reg [31:0] in_del;
reg [31:0] out_del;
always # (posedge clk)
begin
in_del<=in;
out_del<=~in & in_del;
if (reset)
out=0;
else
begin
for (i=0; i<32;i=i+1) begin
if (out_del[i])
out[i]=out_del[i];
end
end
end
endmodule
my output

Answer 1

First about your code.
it cannot be compiled. The out must be a reg in order to be assignable within the always block.
using non-blocking assignment in out_del <= in & in_del will cause a one-cycle delay for the if (out_del) comparison. Non-blocking assignments schedule lhs assignment after the block gets evaluated. The rule of thumb is to always use blocking assignments for intermediate signals in the sequential block.
because of the above and because of the in & in_del, this cannot be synthesized, or at least it cannot be synthesized correctly.
you violate industry practices by using the blocking assignment on the out signal. The rule of thumb is to always use non-blocking assignments for the outputs of the sequential blocks.
the code just does not work :-(
If I understood your requirement correctly the following code does it:
module top_module (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out );
reg lock;
always # (posedge clk)
begin
if (reset) begin
lock <= 0;
out <= 0;
end
else if (lock == 0)
begin
out <= in;
lock <= 1;
end
end
endmodule
Just use the lock signal to allow updated. And yes, here is a simple test bench to check it:
module real_top();
reg clk, reset;
reg [31:0] in;
reg [31:0] out;
top_module tm(clk, reset, in, out);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
integer i;
initial begin
in = 0;
reset = 1;
#7 reset = 0;
for (i = 1; i < 5; i++) begin
#10 in = i;
#10 reset = 1;
#10 reset = 0;
end
$finish;
end
initial
$monitor(clk, reset, in, out);
endmodule