Fastest way to react to an external trigger signal - verilog

Question

An external trigger signal is sent to the FPGA. The trigger signal should be accepted only if and1 and and2 are also high at the time the trigger is received. If the trigger is accepted, a 10 microsecond duration trigger out pulse should be created. The goal is to try and minimise the time that the FPGA takes to accept/reject this external trigger signal.
module trigger(
input CLK,
input trigger,
input and1,
input and2,
output triggerOut,
);
The first attempt at a solution was the following;
assign triggerOut = trigger & and1 & and2;
The reaction time is fast but I don't think this allows the 10 microsecond trigger duration to be implemented.
The current solution is the following;
always #(posedge CLK) begin
if(trigger & and1 & and2)
triggerOut <= 1;
end
This solution allows a counter to be added, which allows the 10 microsecond trigger pulse to be implemented. The caveat is that now the reaction time to the external trigger is tied to the frequency of CLK. The reaction time can be improved by increasing the CLK frequency, but there is a limit to how high CLK can be increased.
Another possible solution may be sensitivity to the changing trigger input;
always #(posedge trigger) begin
if(trigger & and1 & and2)
triggerOut <= 1;
end
I have read that this may be bad practice. It was not clear to me why using #(posedge CLK) is preferred to #(posedge trigger). What defines the reaction time of the FPGA to a sensitivity like #(posedge trigger)? I suppose this must still be somehow tied to CLK - is this approach potentially any faster?
Are there any better approaches to improve the reaction time to the trigger input?

Answer 1

It's difficult to reach that goal without resorting to asynchronous logic. Fortunately, recent FPGAs have level triggered latches as primitives, so incomplete combinational always blocks not always are a bad practice.
OTOH, the 10us width triggerOutput signal needs a synchronous clock to count time, but this timer will, at a first approach, be triggered by an asynchronous input. That will surely pose a problem of cross domain clocking and the trivial solution (synchronizing with two flip-flops) will introduce some latency so the 10us pulse may not start at the same time that trigger is internally accepted, and/or be exactly 10us width. To avoid the metastability issue with triggerOutput, it can be used as an asynchronous reset signal for the 1 to 10 counter.
That all said, this module is a implementation of an asynchronous approach to your trigger detector and acceptor:
module detect_trigger (
input wire clk, // let's say it's 1 MHz (period = 1us)
input wire trigger,
input wire and1,
input wire and2,
output reg triggerOut
);
reg [3:0] cnt = 4'd0;
initial triggerOut = 1'b0;
always #* begin
if (cnt >= 4'd11)
triggerOut = 1'b0;
else if (trigger && and1 && and2)
triggerOut = 1'b1;
end
always #(posedge clk or negedge triggerOut) begin
if (triggerOut == 1'b0)
cnt <= 4'd0;
else if (cnt < 4'd11)
cnt <= cnt + 4'd1;
end
endmodule
A test bench module could be as this:
module tb;
reg clk;
reg trigger;
reg and1, and2;
wire triggerOut;
detect_trigger uut (
.clk(clk),
.trigger(trigger),
.and1(and1),
.and2(and2),
.triggerOut(triggerOut)
);
initial begin
$dumpfile ("dump.vcd");
$dumpvars(1, tb);
clk = 1'b0;
and1 = 1'b0;
and2 = 1'b0;
trigger = 1'b0;
repeat (5) begin
#3023;
and1 = 1'b1;
#2419;
and2 = 1'b1;
#1865;
and1 = 1'b0;
and2 = 1'b0;
end
$finish;
end
always begin
clk = #500 ~clk;
end
always begin
trigger = 1'b0;
#1753;
trigger = 1'b1;
#2;
end
endmodule
The output of this test bench is as follows:
You can modify and run the above design with EDA Playground here:
https://www.edaplayground.com/x/3SGs