Making a target out-of-date if compiler options differ respect to the previously used ones - linux

Question

Consider the following directory tree for a made-up toy example that illustrates the problem to solve:
- Makefile
- lib.c
+ foo/
|-- config.mk
+ bar/
|-- config.mk
Content of foo/config.mk:
CFLAGS += -DFOO
Content of bar/config.mk:
CFLAGS += -DBAR
Calling make with Makefile for the targets foo and bar results in the files foo/config.mk and bar/config.mk being included (by means of the include directive), respectively, and lib.o being built, i.e.:
# build lib.o with the macro FOO defined
$ make foo
# build lib.o with the macro BAR defined
$ make bar
# build lib.o with both the macros FOO and BAR defined
$ make foo bar
$ make bar foo
The default rule for building lib.o uses the variable COMPILE.c, which is defined (according to the output obtained by calling make with the option --print-data-base) as:
COMPILE.c = $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
The expansion of COMPILE.c depends, among other things, on the value of the variable CFLAGS, which, in turn, depends on whether foo/config.mk or bar/config.mk were included, since these makefiles modify the CFLAGS variable.
What I would like to achieve is to treat the target lib.o as an out-of-date target if the expansion of the variable COMPILE.c that is currently used is not the same as the one used for the previous build of lib.o. For example:
$ make foo
# It shouldn't rebuild anything since lib.o should be up-to-date
$ make foo
# It should rebuild lib.o since it should be out-of-date
$ make bar
# It should rebuild lib.o since it is again out-of-date
$ make foo bar
# It shouldn't rebuild lib.o since it is up-to-date
$ make bar foo
This solution explains how I've implemented this behaviour so far. Any suggestion is welcomed.

Answer 1

I would dump the variable's value in another included makefile and check whether the current value is different from the one from the included makefile. Something like:
ifeq ($(filter foo,$(MAKECMDGOALS)),foo)
include foo/config.mk
endif
ifeq ($(filter bar,$(MAKECMDGOALS)),bar)
include bar/config.mk
endif
-include old_compile.mk
COMPILE.c = $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
ifneq ($(COMPILE.c),$(OLD_COMPILE.c))
FORCE := force
endif
lib.o: lib.c $(FORCE)
$(COMPILE.c) $< -o $#
echo 'OLD_COMPILE.c := $(COMPILE.c)' > old_compile.mk
.PHONY: foo bar all force
foo bar all: lib.o
Demo:
$ make foo
cc -DFOO -c lib.c -o lib.o
echo 'OLD_COMPILE.c := cc -DFOO -c' > old_compile.mk
$ make foo
make: Nothing to be done for 'foo'.
$ make foo bar
cc -DFOO -DBAR -c lib.c -o lib.o
echo 'OLD_COMPILE.c := cc -DFOO -DBAR -c' > old_compile.mk
make: Nothing to be done for 'bar'.
$ make bar foo
make: Nothing to be done for 'bar'.
make: Nothing to be done for 'foo'.

Answer 2

Here's my crude mockup that encodes compiler/linker flags directly in filenames. It's just an idea, an actual implementaation should be a bit more robust.
empty:=
space:= $(empty) $(empty)
comma:= ,
LDFLAGS_NS=$(subst $(space),$(comma),$(LDFLAGS))
CFLAGS_NS=$(subst $(space),$(comma),$(CFLAGS))
EXEDIR=./test-exedir-cflags=$(CFLAGS_NS)-ldflags=$(LDFLAGS_NS)
EXEDIR_PAT=./test-exedir-*
OBJDIR=./test-objdir-cflags=$(CFLAGS_NS)
OBJDIR_PAT=./test-objdir-*
test.exe: $(EXEDIR)/test.exe
rm -f test
ln -s $< $#
$(EXEDIR)/test.exe: test.o
rm -rf $(EXEDIR_PAT)
mkdir $(EXEDIR)
cc $(LDFLAGS) -o $# $<
test.o: $(OBJDIR)/test.o
rm -f test.o
ln -s $< $#
$(OBJDIR)/test.o: test.c
rm -rf $(OBJDIR_PAT)
mkdir $(OBJDIR)
cc -c $(CFLAGS) -o $# $<
Tested with a hello world test.c file and these commands:
make test.exe
make test.exe
make test.exe CFLAGS="-g -Wall"
make test.exe CFLAGS="-g -Wall"
make test.exe

Answer 3

My approach, so far, consists of generating a file, cc-options-dump, with the contents of the expansion of the COMPILE.c variable everytime lib.o is built.
The MD5 hash resulting of the expansion of the current COMPILE.c variable is compared against the one that was used for the previous build, i.e., the one whose contents are stored in the file cc-options-dump, if any (i.e., if the file does exist).
.PHONY: foo bar require-rebuild cc-options-dump
# include the xxx/config.mk files
# sort built-in function to make it independent of the order (i.e., "foo bar" or "bar foo")
$(foreach opt,$(sort $(MAKECMDGOALS)),$(eval include $(opt)/config.mk))
# obtain the MD5 hash of the previously used flags
ifneq (,$(wildcard cc-options-dump))
prev-cc-options-hash := $(shell md5sum cc-options-dump | cut -f1 -d' ')
endif
# obtain the MD5 hash of the current flags
curr-cc-options-hash := $(shell echo "$(COMPILE.c)" | md5sum | cut -f1 -d' ')
# Do these hashes differ?
ifneq ($(prev-cc-options-hash),$(curr-cc-options-hash))
# keep track of the fact that a rebuilt needs to be triggered
does-need-rebuild := require-rebuild
# just for displaying information
$(info Rebuild required)
else
$(info Rebuild not required)
endif
# make both targets foo and bar dependent on the file with the flags
# so that it has to be generated, since it is a phony target as well
foo bar: cc-options-dump
# lib.o has now an additional prerequisite for determining whether it need to be rebuilt
lib.o: $(does-need-rebuild)
# save the used compiler flags for comparing them with the future flags
cc-options-dump: lib.o
#echo '$(COMPILE.c)' >$#
The behaviour of this makefile when calling make for the targets foo and/or bar corresponds, as far as I can see, to the desired one:
$ make foo
Rebuild required
cc -DFOO -c -o lib.o lib.c
$ make foo
Rebuild not required
$ make bar
Rebuild required
cc -DBAR -c -o lib.o lib.c
$ make bar
Rebuild not required
$ make foo bar
Rebuild required
cc -DBAR -DFOO -c -o lib.o lib.c
$ make bar foo
Rebuild not required
The use of the sort built-in function is crucial for the last two cases above to work correctly.
It would be great if someone could come with a more elegant solution.