Closed. This question needs debugging details. It is not currently accepting answers.
Edit the question to include desired behavior, a specific problem or error, and the shortest code necessary to reproduce the problem. This will help others answer the question.
Closed yesterday.
Improve this question
i tried to do it in two ways, and each time i got stuck by the same problem Error (10031): Net "copy_data_in[183]" at RotateText.sv(16) is already driven by input port "data_in[183]", and cannot be driven by another signal.
Hi , i have input of 23 elements that each one is 8 bits.i have output of 6 elements that each one is 8 bits.The input should get change each time. in the end it should be like circular printing. Excuse me but ENABLE should be CLK.
i tried to do it in two ways, and each time i got stuck by the same problem Error (10031): Net "copy_data_in[183]" at RotateText.sv(16) is already driven by input port "data_in[183]", and cannot be driven by another signal.
This first try :
module RotateText( data_in,HEX0S,HEX1S,HEX2S,HEX3S,HEX4S,HEX5S,ENABLE);
input [7:0] data_in [22:0];
input ENABLE;
output reg [7:0] HEX0S;
output reg [7:0] HEX1S;
output reg [7:0] HEX2S;
output reg [7:0] HEX3S;
output reg [7:0] HEX4S;
output reg [7:0] HEX5S;
reg [7:0] tmp;
reg [7:0] copy_data_in [22:0];
reg [7:0] tmp2;
integer i;
integer j=0;
always#(posedge ENABLE)begin
if(j==0)begin
for(i = 0; i < 23; i=i+1) begin
copy_data_in[i] <= data_in[i];
end
end
HEX5S<=copy_data_in[22];
HEX4S<=copy_data_in[21];
HEX3S<=copy_data_in[20];
HEX2S<=copy_data_in[19];
HEX1S<=copy_data_in[18];
HEX0S<=copy_data_in[17];
tmp<= copy_data_in[22];
copy_data_in[22:1]<=copy_data_in[21:0];
copy_data_in[0]<=tmp;
j=j+1;
end
endmodule
This is another approch :
module RotateText( data_in,HEX0S,HEX1S,HEX2S,HEX3S,HEX4S,HEX5S,ENABLE);
input [183:0] data_in ;
input ENABLE;
output reg [7:0] HEX0S;
output reg [7:0] HEX1S;
output reg [7:0] HEX2S;
output reg [7:0] HEX3S;
output reg [7:0] HEX4S;
output reg [7:0] HEX5S;
reg [7:0] tmp;
reg [183:0] copy_data_in;
integer i;
integer j=0;
integer index;
assign copy_data_in=data_in;
always#(posedge ENABLE)begin
HEX5S<=copy_data_in[183:176];
HEX4S<=copy_data_in[175:168];
HEX3S<=copy_data_in[167:160];
HEX2S<=copy_data_in[159:152];
HEX1S<=copy_data_in[151:144];
HEX0S<=copy_data_in[143:136];
tmp<=data_in[183:176];
copy_data_in<=copy_data_in<<8;
copy_data_in[7:0]<=tmp;
end
endmodule
glad to get help .
The post has a circular shift register (sr).
An sr accepts input from the previous stage or from a module input for loading; not both at the same time. Loading & shifting are mutually exclusive behaviors in the same clock clock cycle. The design needs a input control signal to decide load or shift.
The posted code errors out, because its trying to drive the sr internally, and from inputs at the same time.
Here is a solution based on the posted code.
Variable load_shiftn determines load or shift .
module rot(
input logic clk,
input [7:0] data_in [22:0],
input logic load_shiftn,
output reg [7:0] HEX0S,
output reg [7:0] HEX1S,
output reg [7:0] HEX2S,
output reg [7:0] HEX3S,
output reg [7:0] HEX4S,
output reg [7:0] HEX5S
);
// internal
reg [7:0] sr [22:0];
always#(posedge clk)begin
if(load_shiftn)
sr <= data_in;
else begin
sr[22:1] <= sr[21:0];
sr[0] <= sr[22];
end
end
always # * begin
HEX5S =sr[22];
HEX4S =sr[21];
HEX3S =sr[20];
HEX2S =sr[19];
HEX1S =sr[18];
HEX0S =sr[17];
end
endmodule
Testbench
module tb ();
bit clk;
logic [7:0] data_in [22:0];
bit load_shiftn;
logic [7:0] HEX0S;
logic [7:0] HEX1S;
logic [7:0] HEX2S;
logic [7:0] HEX3S;
logic [7:0] HEX4S;
logic [7:0] HEX5S;
always #5 clk = !clk;
initial begin
#270;
$finish;
end
rot u1 (.*);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
initial begin
foreach(data_in[i])
data_in[i] = i;
end
initial begin
#(posedge clk)
load_shiftn <= 1;
repeat(2) #(posedge clk);
load_shiftn <= 0;
end
endmodule
Waves
I'm trying to design a parallel to serial converter. But my final waveform look like this:
Here is my code, thanks in advance.
module parallel2serial#(parameter size=4)(pin, clk, load, rst, sout, finish);
input [size-1 :0] pin;
input clk, rst, load;
output reg finish;
output sout;
reg [2:0]count;
reg [size-1 :0] data;
reg dout;
always#(posedge clk)begin
if(!rst)begin dout<=0; end
else if(!load)begin
data<=data>>1;
dout<=data[size-1];
end
else data<=pin;
end
always#(posedge clk)begin
if(!rst)begin count<=0; finish<=0;end
else begin
if(count==2'b11) begin count<=0; finish<=1;end
else begin count<=count+1; finish<=0;end
end
end
assign sout=dout;
endmodule
There's at least one mistake. You're shifting data towards the least significant bit (to the right), while taking the output from the most significant bit. You should either output lsb instead of msb, or change the direction of register shifting.
I'm having difficulty figuring out how to assign the value of temp to the out. I searched the web for an answer and tried all kinds of things but still cannot get the output assigned. Here's the code:
module Reg8bit(
input CLK,
input En,
input CLR,
input [7:0] in,
output [7:0] out
);
reg[7:0] temp;
always #(posedge CLK)
begin
if (En)
begin
if (CLR)
out = 8'b0000_0000;
else
out = in;
end
end
assign out = tempQ;
endmodule
Edit: temp should be tempQ, sorry for the typo
You probably meant to write
module Reg8bit(
input CLK,
input En,
input CLR,
input [7:0] in,
output reg [7:0] out // out is a variable, not a wire
);
always #(posedge CLK)
begin
if (En)
begin
if (CLR)
out <= 8'b0000_0000; // use Non-blocking assignments
else
out <= in;
end
end
endmodule
Your code doesn't make much sense. You are assigning to out twice and your not using your temp register.
You probably meant to write something like this:
reg[7:0] temp;
always #(posedge CLK)
begin
if (En)
begin
if (CLR)
temp <= 0;
else
temp <= in;
end
end
assign out = temp;
Its usually (not always) considered good practice to use nonblocking assignments in always blocks. I think in this case you can even do this without the temp register.
The LHS of the assign statement should always be a wire. You have declared out as a reg and it's good to use a reg data type in the LHS inside an always block.
I am attempting to use an FPGA as a shift register to some LEDs with pwm, but ran into an error while trying to assign a reg containing the value shifted in to an output variable. When I upload it to the FPGA(i'm using the mojo by embedded micro), it does nothing. when I use the simulator, it reports that all of the output variables are never assigned and have the value of X, while all the other variables inside of the module work just fine. here is my code for the shifting module:
module shifting(
input clk,
input shiftingpin,//data to be shifted in
input rst,
output done,
output [3:0]data//pwm compare value output
);
reg [2: 0] ctr_d, ctr_q;
reg don;
reg [3:0]datas;
always #(*) begin
if(ctr_q == 3'b100) begin
ctr_d[2:0] = 3'b0;
don = 1'b1;
end else begin
ctr_d = ctr_q + 1'b1;
don = 1'b0;
end
end
always #(posedge clk) begin
datas[ctr_q] = shiftingpin;// assign value to the output
if (rst) begin
ctr_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
end
end
assign data = datas;
assign done = don;
endmodule
done tells the containing module when to update and assign the value to pwm.
If I understood the question correctly you have a syntax error when trying to drive ports from within always blocks.
When declaring ports they are typically wire by default which can only be driven by ports or assign. Resulting in the code below
module shifting(
input clk,
input shiftingpin,
input rst,
output done,
output [3:0] data
);
reg don;
reg [3:0] datas;
assign done = don;
assign data = datas;
Solution
The solution is to define ports as reg, logic is preferred if you can support System Verilog.
logic will effectively switch between wire and reg as required to make refactoring code easier.
module shifting(
input clk,
input shiftingpin,
input rst,
output reg done,
output reg [3:0] data
);
always #(posedge clk) begin
data[ctr_q] <= shiftingpin; // <-- data port used directly
//...
NB: shift registers can be done with just
always #(posedge clk) begin
datas[3:0] <= {datas[2:0], shiftingpin};
I am working on designing a LC-3(Little Computer) CPU. I have designed PC unit, Control Unit(as Finite State Machine), Instruction Memory, ALU unit and Data Memory in Modules. There is also a Register File unit which works as Main, module calls are done in this unit.
I want the program to work as when PCread is 1, get the variable that going to be assigned to out from in variable, and when PCwrite is 1, just increment the out variable. out is the address that sent to the Instruction Memory.
The problem is when I simulate, instruction never loads to the Instruction Memory. Because PCwrite does not work for the first state of the Control Unit, because I reset both PCread and PCread variables in the first state. I do this because I do not want the instruction to load until one instruction finishes it work. I could not find a way to handle this.
I know if this is solved, processor will work because when I try it for one instruction with initialized values, it works.
module reg_fileandMain();
parameter B=16, W=3;
reg Clk;
wire wr_en;
wire [W-1:0] w_addr, r_addr1, r_addr2;
wire [B-1:0] inData;
wire [B-1:0] r_data1;
wire [B-1:0] r_data2;
wire [B-1:0] address;
wire Dataout;
wire InsMemRead;
reg [15:0] extended, mux1out, mux2out, mux3out, mux4out, mux5out;
wire ALUout, incrementer;
wire [15:0] instruction;
reg [B-1:0] array_reg[2**W-1:0];
wire mux1,mux3,mux4,mux5;
wire [1:0] mux2;
initial begin
mux5out=16'hFFFF;
end
wire MemRead,PCwrite,ALUcontrol,MemWrite,PCread;
always#(posedge Clk)
begin
if(wr_en)begin
array_reg[w_addr]<=inData;
end
end
assign r_data1=array_reg[r_addr1];
assign r_data2=array_reg[r_addr2];
controlUnit controlUnit0(Clk,instruction,mux1,mux2,mux3,mux4,mux5,InsMemRead,MemRead,PCwrite,wr_en,ALUcontrol,MemWrite,PCread,r_addr1,r_addr2,w_addr);
PCunit PCunit0(Clk,PCwrite,PCread,mux5out,address);
DataMem DataMem0(Clk,mux2out,r_data1,MemRead,MemWrite,Dataout);
ALU ALU0(mux1out,r_data2,ALUout,ALUcontrol);
InstructionMemory InstructionMemory0(Clk,address,InsMemRead,instruction);
always #* begin
if(mux1)begin
extended = { {11{instruction[4]}}, instruction[4:0] };
mux1out=extended;
end
else begin
mux1out=r_data1;
end
if(mux2==2'b00)begin
mux2out=ALUout;
end
else if(mux2==2'b01)begin
extended = instruction[8:0];
mux2out=extended;
end
else if(mux2==2'b11)begin
extended = instruction[8:0];
mux2out=extended;
end
if(mux3)begin
mux3out<=mux2out;
end
else begin
mux3out<=Dataout;
end
if(mux4)begin
mux4out<=address;
end
else begin
mux4out<=mux3out;
end
if(mux5)begin
mux5out<=address;
end
else begin
mux5out<=mux3out;
end
end
assign inData=mux4out;
always begin
#20 Clk<=0;
#20 Clk<=1;
end
endmodule
module controlUnit(Clk,in,mux1,mux2,mux3,mux4,mux5,InsMemRead,MemRead,PCwrite,WE,ALUcontrol,MemWrite,PCread,rd1,rd2,wr);
input Clk;
input [15:0] in;
output reg mux1,mux3,mux4,mux5,InsMemRead,MemRead,PCwrite,WE,ALUcontrol,MemWrite,PCread;
output reg [1:0] mux2;
reg [3:0] state,stateNext;
reg counter;
output wire [2:0] rd1,rd2,wr;
initial begin
state=4'b0000;
stateNext=4'b0001;
MemRead=0;
PCwrite=1;
end
assign rd1=in[2:0];
assign rd2=in[8:6];
assign wr=in[11:9];
always #* begin
if (state==4'b0000)begin
stateNext=4'b0001;
PCwrite=0;
PCread=0;
end
if(state==4'b0001)
begin
InsMemRead<=1;
if(in[15:12]==4'b0100)begin
stateNext=4'b0100;
InsMemRead=1'b1;
end
else if( in[15:12]==4'b1000)begin
stateNext=4'b0100;
InsMemRead=1;
end
else if(in[15:12]==4'b0010)begin
stateNext=4'b0010;
InsMemRead=1;
end
else if(in[15:12]==4'b1100)begin
stateNext=4'b1100;
InsMemRead=1;
end
else if(in[15:12]==1010)begin
stateNext=4'b1010;
InsMemRead=1;
end
end
else if(state==4'b0100)begin
stateNext=4'b0101;
end
else if(state==4'b0101)begin
stateNext=4'b0000;
mux3=0;
mux4=0;
WE=1;
mux2=2'b01;
MemRead=1;
mux5=1;
PCwrite=1;
end
else if(state==4'b1000)begin
stateNext=4'b0000;
mux1=in[5];
ALUcontrol=0;
mux3=1;
mux4=0;
WE=1;
PCwrite=1;
end
else if(state==4'b0010)begin
stateNext=4'b0000;
mux1=in[5];
ALUcontrol=1;
mux3=1;
mux4=0;
WE=1;
PCwrite=1;
end
else if(state==4'b1100)begin
stateNext=4'b0000;
mux2=2'b01;
MemWrite=1;
PCwrite=1;
end
else if(state==4'b1010)begin
stateNext=4'b0000;
mux2=2'b11;
mux3=1;
mux5=0;
PCread=1;
end
end
always #(posedge Clk) begin
state = stateNext;
end
endmodule
module PCunit(Clk,PCwrite,PCread,in,out);
input Clk,PCread,PCwrite;
input wire [15:0] in;
output reg [15:0] out;
always #(posedge Clk) begin
if(PCwrite)
begin
out<=out+1;
end
else
begin
if(PCread)
begin
out<=in;
end
end
end
endmodule
module ALU(in1,in2,ALUout,ALUcontrol);
input ALUcontrol;
input wire [15:0] in1, in2;
output reg [15:0] ALUout;
always #* begin
if(ALUcontrol)
ALUout = in1 + in2;
else
ALUout = in1 & in2;
end
endmodule
module DataMem(Clk,AddrReg,in,MemRead,MemWrite,out);
input Clk, MemRead, MemWrite;
input [15:0] AddrReg, in;
output reg [15:0] out;
reg[15:0] Mem[2**9:0];
always #(posedge Clk) begin
if(MemWrite)begin
Mem[AddrReg]=in;
end
end
always #* begin
if(MemRead) begin
out=Mem[AddrReg];
end
end
endmodule
module InstructionMemory(Clk,address,InsMemRead,instruction);
input Clk;
input [15:0] address;
input InsMemRead;
output reg [15:0] instruction;
reg [15:0] InstructionMemory [15:0];
initial begin
$readmemh("AssemblerOutput.hex", InstructionMemory);
end
always#(posedge Clk)begin
if(InsMemRead)
instruction=InstructionMemory[address];
end
endmodule
Always use #* for sensitivity lists for combinational logic. Change:
always #(MemRead) begin
to:
always #* begin
Your always block is not sensitive to changes in AddrReg.
I found that one way to solve this is sending a signal from the PC unit to control unit that the instruction adress is sent to instruction memory with an output reg variable, and check if this variable is changed in control unit, if it is, reset the PCwrite variable. Thanks to all tried to help.