I'm trying to simulate a RISCV based processor on Synopsys VCS with RTL design (verilog). I would like to change the voltage dynamically while the simulation is running. Is there any tool in Synopsys that can be used for performing dynamic voltage scaling in a microprocessor. Or is it possible to do so in testbench?
There is no concept of analog values such as voltage in verilog or VHDL. Just digital signals and simple timing.
Analog simulations are done in other languages like SPICE.
Related
I am curious to learn about the technology which is used in generating software clock in simulators. The frequency of my machine is only ~2.4GHz but I can generate up to 500THz clock using a simulator(Refer below system Verilog snippet ).
`timescale 1fs/1fs;//This is the minimum time-unit and precision that can be used to generate 500THz clock
module temp();
bit clk_b;
always #1 clk_b =~ clk_b ;
endmodule
Is this higher frequency just a software illusion or does it have any link with CPU crystal oscillator?
The simulation does not "run" in realtime. So it will compute the result for the steps and if it is done it is done. Which means that the ratio between number of required steps (as well as problem complexity) and your computer performance will define how much time the simulation will need to finish. The timescale setting of the simulation is just what it says: a way to relate the simulation steps into a time(scale).
So it is really an "illusion" if you want to call it so.
SystemVerilog is a HVL i.e. a Hardware Verification Language. It is (mostly) used to verify hardware designs.
The main purpose of the language is to provide a platform where one can create logic to verify the DUT by running simulations i.e. generating different operating conditions for the DUT and checking how it behaves under each condition. But this does not necessarily mean that DUT is supposed to operate in such extreme conditions generated by the SystemVerilog testbench.
When you are generating 500THz clock from your testbench and checking the behaviour of your DUT, you are making sure that the DUT is not (virtually) going to break down even in such extreme conditions. But please note that this is just a virtual environment you have created and not the actual environment under which the DUT once synthesised is supposed to operate.
If the maximum frequency of the machine (or DUT) is ~2.5GHz, it is supposed to operate at that frequency in the actual environment, but just out of curiosity you can even check operation of DUT with different input clock frequencies by generating different simulations.
Hope it helps!
I have been working on a class project using Verilog. I had to create a circuit and then calculate the power that the circuit uses. I have been trying to do it using Xpower Analyzer I follow the instruction to create the vcd file, compile and synthesize the code using Xilinx ISE 14.7 . Everything goes well until the result shows up. I received 0 power consumption from the clock. I try to constrains the clock and it only give me a increment in dynamic power from 0 to 0.009, but not luck in the clock. Also, I try Xpower in my personal computer and at my university computer lab, so I don't think that it is a software bug.
Moreover, I have try different design such as a simple alu, register etc. Nonetheless, I still getting the same power result.
More information:
Testbench runs well and does what I want
I declare clock like: module toptrafficlight(
clock,rst,output );
List item: I have constrained the clock to 20ns
Timing phase = 0. After synthesis (not sure what this means)
Warrnings from:
HDLCompiler:413 - Line 86: Result of 5-bit expression is truncated to fit in 4-bit target.
PhysDesignRules:372 - Gated clock. Clock net main_gated_clk is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Power result from Xpower Analyzer
My questions are?
is it a way to setup the clock? which I think might be the cause of the problem
is there anything else needed to be done beside getting the VCD file and synthesize the code?
any other ideas, examples or tutorial?
The screenshot shows that the design is very small, so it's not a big surprise for clock power to be smaller than 1mW. Xilinx also provides an Excel sheet for power estimation. It can be used for a quick tryout to see what circumstances make the clock power significant.
Xilinx Power Estimator (XPE)
In FPGA programming, what is the point of using the create_clock command in the XDC (or UCF) file? Let's say I have a clock port CLK that is assigned to a physical pin (which is my clock), in the XDC (or UCF) file. Why can't I just go ahead and use this CLK pin in my top level HDL? Why do I need to add something like this:
create_clock -name sys_clk_pin -period "XXX" [get_ports "CLK"]
Also, let's say I have a main clock "CLK" and some other clocks which I generate in HDL. Do I have to use "create_clock" for all the minor clock in XDC too?
I don't get this whole "create_clock" thing. Any help or direction is much appreciated.
Thanks
Design constraints, as the name suggests, are used in order to define additional constraints of your design, which can't be captured from HDL description.
Lets take create_clock command as an example. You specified the clock pin in your HDL description, why isn't this enough? The reason is that clock signal is not a usual signal - it is used as a reference signal by a synchronous logic (flip-flops).
I suppose you're familiar with "propagation delay" (through logic gates) concept. You want to make sure that all signals originating at one flop and sampled at the other will be able to propagate during a single clock cycle. Now, the total propagation delay you can know right after synthesis because each logic gate in FPGA has associated propagation delay (just sum these up). But how your analysis tools know what is the maximal allowed propagation delay? You do not specify these constraints in HDL, right? This is one of the cases where the frequency you specified with create_clock command will be used - it will be converted to period, and an analysis tool will warn you if any of the combinatorial paths in your design takes longer to propagate than clock's period.
The above example describes one of the actions performed by Static Timing Analysis (STA) tools in which "design constraints" are employed.
Another kind of tools which make extensive use of design constraints is Clock Domain Crossing (CDC) tools. These tools employed in designs containing more than one clock. The CDC concepts are described brilliantly here
In case you take one clock and generate another one from it (clock divider for example) you want to make CDC tool aware of this, because the fact that these clocks are related is important. Your way to inform CDC tool that the clocks are related is to use create_generated_clock constraint.
NOTE: the above examples are basic and by no means comprehensive.
Im doing a dsp project and i want to take an anolog file and convert it to a digital output using a microconroller attached to a ADC on a dsp board. How would i program this in c?
Pretty much its as simple as that, atleast i think.
This is what i need.
Input --------- Output
Angolog --> Digital
Digital --> Anolog
You really need to clarify your question. Like what do you mean by analog file? File systems are binary from a programming perspective, sure the media is magnetic or other technologies and there is analog involved. An ADC goes from Analog to Digital, so it is an an analog input not a digital output.
ADC analog to digital converter, takes analog inputs to the device and converts them to digital so you can use them inside the chip, program, save to files, etc.
DAC digital to analog converter, takes digital values and converts them to analog outputs.
In both cases you need to look at the specific details for the chips and the board. From a programming perspective if nothing else you need to look into the details for the ADC and or DAC. Microcontrollers having an ADC is not uncommon, but you need to read up on how to get the ADC on that microcontroller to initiate a sample, how to know when the sample has completed and how to read the digital data once the sample has been taken. DACs are often external, sometimes serial, so you may have to bit bang spi or i2c or look into what hardware the microcontroller might have for speaking spi or i2c or if there is a dac in the microcontroller, how to use it (what registers to write, etc).
If you have a specific publicly available microcontroller board, for example an eval board, then that makes it much easier for folks here or elsewhere to show you where to look for the schematics, data sheets, etc. Otherwise, even knowing exactly which microcontroller and what I/O pins are used, would be helpful when asking such a question. There are probably lots of example programs out there that could be borrowed from. And it could be as simple as a few lines of C to an existing library, or as complicated as many lines of C with interrupt service routines, and possibly some assembler.
This is extremely dependent on your hardware and there's no information in the question that would enable a real answer.
In general, you should see the documentation for your system, especially the AD/DA parts. There should be good examples. If there's a particular problem, post a more specific question.
Is there any straight forward way to implement an all digital phase lock in synthesizable Verilog? Everything (including the VCO) should be synthesized. The signals I'm looking to lock to are ~0.1-1% of the system clock frequency. I am using one that I've reconstructed from 1980's IEEE papers, but it doesn't behave as well as advertised.
For simplicity, the lock can work on a binary pulse signal.
In FPGA designs I normally use the built in DCMs, or PLLs.
The Cyclone 2 has up to 4 PLLs built in.
Have a look at PLLs in Cyclone 2.