I need to initialize arrays in generated instances via generate block in Verilog. I'm trying to use the syntax below, however, I get an error as
External reference foo[0].bar.array[0] remains unresolved.
in Xilinx ISE.
integer i, j;
initial begin
// initialization of arrays
for(i=0; i<(2**7); i=i+1) begin
valid_array[i] = 0;
for(j=0; j<N; j=j+1) begin
foo[j].bar.array[i] = 0;
end
end
end
This is my generate block:
genvar jj;
generate
for(jj = 0; jj < N; jj = jj + 1) begin : foo
Memory_v3
#(
.ADDRESS_WIDTH(INDEX),
.DATA_WIDTH(TAG)
) bar
(
.clock(clock),
.we(we),
.addr_a(addra),
.addr_b(addrb),
.din(din),
.dout(dout)
);
end
endgenerate
What is the correct way to do this?
the problem is that foo block gets resolved at compile time. So, the names like foo[0], foo[1] are pre-generated and are compile-time names, they not work with dynamic index resolution at run-time. Therefore foo[j] will not work.
the solution in this case is to use another generate block to initialize them. Something like the following.
generate
for(jj = 0; jj < N; jj = jj + 1) begin : foo_init
initial begin
// initialization of arrays
for(i=0; i<(2**7); i=i+1) begin
foo[jj].bar.array[i] = 0;
end
end
end
endgenerate
Same story is with array of instances.
FOO bar[3:0](); // array of instances
int i,j;
generate
for(jj = 0; jj < 4; jj = jj + 1) begin : foo_init
initial begin
for(i=0; i<(2**7); i=i+1) begin
bar[jj].array[i] = 0;
end
end
end
endgenerate
BTW, in system verilog you can avoid using generate/endgenerate pairs:
Related
I thought of generating clock using genvar like below:
reg [7:0]clk;
genvar i;
generate
for (i=0; i < 7; i++) begin
#1 clk[i]=~clk[i];
end
endgenerate
I am getting an error:
error: near "#": syntax error, unexpected '#'
How can we resolve it? Can I use delays inside generate block?
I feel it isn't necessary to have a generate, you can use the for loop directly in an always block:
reg [7:0] clk;
integer i;
always begin
#1;
for(i = 0; i < 7; i = i + 1)
clk[i] = ~clk[i];
end
Nevertheless, if all the bits are toggled at the same time, you can simplify it with:
always
#1 clk = ~clk; //..bitwise invert the array
Yes, generate blocks support delays. To fix your problem, use a procedural always block:
reg [7:0] clk;
genvar i;
generate
for (i=0; i < 7; i++) begin
always #1 clk[i]=~clk[i];
end
endgenerate
It looks like OP wanted to have a sequential delay model. In this case the code should look like this:
always begin
for(i = 0; i < 7; i = i + 1)
#1 clk[i] = ~clk[i];
end
I'm trying to assign I/O vectors inside a for loop in order to save space. I am unsure if this is not possible or I am running into a syntax issue.
I have tried using generate and am still running into issues
My current code is as follows:
module Test_IO
(
output [7:0] led,
input [7:0] sw
);
genvar i;
generate
for(i = 0;i < 8; i = i + 1)
{
assign led<i> = sw<i>;
}
endgenerate
endmodule
I was hoping to save space instead of having to use 8 assign statements but I have been receiving the following error:
ERROR:HDLCompiler:806 -
"C:/Users/Danie/Desktop/Digilent/Projects/Test_IO/Test_IO.v" Line 31:
Syntax error near "{".
I am assuming you are using verilog. Try the below code. You really don't need a genvar for the assignment you are doing.
module Test_IO
(
output [7:0] led,
input [7:0] sw
);
genvar i;
generate
for(i = 0;i < 8; i = i + 1)
assign led[i] = sw[i];
endgenerate
endmodule
Alternatively you may try the below one too
module Test_IO
(
output reg [7:0] led,
input [7:0] sw
);
integer i;
always#(*)
begin
for(i=0;i<8;i=i+1)
led[i] = sw[i];
end
endmodule
Your problem is syntax. In verilog use begin and end, not { and }
genvar i;
generate
for(i = 0;i < 8; i = i + 1)
{
assign led<i> = sw<i>;
}
endgenerate
becomes
genvar i;
generate
for(i = 0;i < 8; i = i + 1) begin
assign led[i] = sw[i];
end
endgenerate
sometimes compilers requires the generate loop to be named using : NAME after begin
genvar i;
generate
for(i = 0;i < 8; i = i + 1) begin : ASSIGN_GEN
assign led[i] = sw[i];
end
endgenerate
Is below sort of generate loop is valid in system verilog.
genvar i,j;
for (i=0,j=5; i<5 && j<10; i++,j++) begin:M1
integer t;
initial begin
t = i*j;
end
endgenerate
Nope. I'm not even sure what the behavior of this code should be, or in what order they execute.
genvar i,j;
for (i = 0; i <5; i++) begin
for (j = 5; j < 10; j++) begin
$display("%d", i*j);
end
end
you don't need 'endgenerate' in the end.
You cannot do much with genvars in your example.
The following code mimics what you asked for, but it might not work with all simulators. It works with synopsys vcs but does not work with icarus.
module g;
genvar i;
for (i=0; i<5; i++) begin:M
if (i == 0) begin:B
parameter j = 5;
end
else begin:B
parameter j = g.M[i-1].B.j + 1;
end
integer t;
initial begin
t = i*B.j;
$display(i, B.j, t);
end
end // block: M
endmodule // g
the idea is to declare the parameter j inside the generate loop so that its value is an increment of the value declared in the previous iteration. You need to add a named block 'B' to declare conditionally.
I'm trying to add a second level of nesting to my generate loop in the following code, but iverilog is throwing an error that the register j is unknown:
../crc.v:119: register ``j'' unknown in crc_tb.U_crc.loop[31].
So is it possible to use multiple genvars in verilog? It looks like j is being interpreted as a register.
Code snippet:
genvar i;
genvar j;
reg [DATA_WIDTH-1:0] temp;
generate
for(i = 0; i < CRC_WIDTH; i= i + 1)
begin : loop
always #(posedge clock or posedge reset)
begin
if (reset)
begin
crc_out[i+:1] = SEED[i+:1];
end
else if (init)
begin
crc_out[i+:1] = SEED[i+:1];
end
else if (data_enable)
begin
if (DEBUG)
$display("\n\nCRC OUT[%0d]\n***************************************************************************", i);
if (REVERSE)
begin
for (j = DATA_WIDTH-1; j >= 0; j = j - 1)
begin : reverse_loop
temp[DATA_WIDTH-1-j] = data[i][j];
end
crc_out[i+:1] <= prev(DATA_WIDTH-1,i,temp,crc_out);
end
else
begin
crc_out[i+:1] <= prev(DATA_WIDTH-1,i,data,crc_out);
end
end
end
end
endgenerate
You can nest multiple generate loops, but your inner generate loop is inside a procedural block of code - that is illegal. Perhapsj should just be a local variable instead of a genvar.
Consider the following function which I would like to parameterize. I have created some parameters to set a width of the input and a corresponding width parameter for the output.
parameter SELECT_WIDTH = 6;
parameter PRIENC_WIDTH = $clog2(SELECT_WIDTH+1);
function [PRIENC_WIDTH-1:0] prienc6;
input [SELECT_WIDTH-1:0] select;
reg [PRIENC_WIDTH-1:0] out;
begin
casex(select)
6'b000001: out = 3'b101; // Is it possible to parameterize the case statement with generate
6'b00001x: out = 3'b100;
6'b0001xx: out = 3'b011;
6'b001xxx: out = 3'b010;
6'b01xxxx: out = 3'b001;
6'b1xxxxx: out = 3'b000;
endcase
prienc6 = out ;
end
end function
Obviously, the casex statement cases will not expand as written.
So I tried the following, which didn't compile correctly indicating unexpected generate found.
function [PRIENC_WIDTH-1:0] prienc_n;
input [SELECT_WIDTH-1:0] select;
reg [PRIENC_WIDTH-1:0] out;
begin
genvar gv_j;
casex(select)
for (gv_j = 0; gv_j < SELECT_WIDTH; gv_j = gv_j + 1)
begin
{{(SELECT_WIDTH-1)-gv_j{1'b0}},1'b1,{gv_j{1'bx}}} : out = (SELECT_WIDTH-1)-gv_j;
end
endcase
prienc_n = out ;
end
end function
I have been able to get the correct behavior using parameterized if's, but it seems like I should be able to parameterize that casex statement. Any thoughts on how to do this? I guess what I will try next is to wrap the casex in the generate loop and create 6 casex statements, each with only one state.
Since you tagged this question with SystemVerilog, I'll show you how to do this without a case statement or generate
function logic [PRIENC_WIDTH-1:0] prienc_n(
input [SELECT_WIDTH-1:0] select);
for (int j = 0; j < SELECT_WIDTH; j++) begin
if (select[SELECT_WIDTH-1]) return j;
select <<=1;
end
// if no 1 found
return ('x); // you did not specify this case
endfunction
If you need to stay in Verilog, it will need an intermediate variable
function reg [PRIENC_WIDTH-1:0] prienc_n(
input [SELECT_WIDTH-1:0] select);
reg [PRIENC_WIDTH-1:0] out;
integer j;
begin
out = {PRIENC_WIDTH{1'bx}}; // what should be returned if no 1 found
for (j = 0; j < SELECT_WIDTH; j = j + 1) begin
if (select[SELECT_WIDTH-1]) begin
out = j;
select = 0;
end
select = select << 1;
end
prienc_n = out;
end
endfunction