Encoder for bitstream audio format to SDIF VHDL - audio

Question

I'm a newbie in VHDL programming, however I'm trying to achieve SDIF encoding from a dsd datastream coming off from an A-D conversion chip.
The dsd stream from the chip features two independent channels (L&R) data flow,
plus a bitclock line.
The SDIF-3 coding scheme states that the channel coding splits each original bit in a 2 'semi-bit' pattern at double the original bitclock rate.
For ex., if the original bit is 0 the pattern gives the original value+it's inverted, so 0-1, if the bit value of the source stream is 1, the pattern is '1-0', and so on...
I was thinking of using a double-edge triggering to do the frequency doubling of the output stream.
So at the rising edge, the encoder output gives the first semi-bit value, and on the falling edge, the encoder outputs the inverted semi-bit to complete the pattern.
Please see the image below on official coding scheme for this format.
I'm not sure if the code is correct, even if it is possible to do it that way.
Unfortunately I have lack of knowledge on how to simulate this.
Any help, suggestion, greatly appreciated.
My code below...
library ieee;
use ieee.std_logic_1164.all;
entity ENCODER1 is
PORT (
clk_in : in std_logic;
data_l : in std_logic;
data_r : in std_logic;
out_l : out std_logic;
out_r : out std_logic
);
end entity ENCODER1;
architecture rtl of ENCODER1 is
signal q0 : std_logic; --output left
signal q1 : std_logic; --output right
signal d0, d1,clk : std_logic ;
begin
p0: process (d0, d1, clk) is
begin
if (clk'EVENT and clk ='1') then --detect source data # rising edge
q0 <= d0;
q1 <= d1;
if (clk'EVENT and clk ='0') then
q0 <= not d0;
q1 <= not d1;
end if;
end if;
end process p0;
end architecture rtl;
sdif encoding

Answer 1

You can't synthesize two edge events.
One solution is to use a mux and select the mux input with your clock:
out <= d0 when clk else not d0;
As you always want to invert the signal you can also use the clock with an exor gate:
out <= d0 xor not clk;
Note that some FPGAs are notoriously bad at using the clock with logic. The clock has to be specially routed and that can increase the skew significantly.
If your signal goes directly to a output port the manufacturers recommended you use a special DDR I/O port. For Xilinx search for the ODDR I/O primitive of the relevant FPGA you are using. It has all the logic inside to do the work for you.