I am working on vivado on a NoC that contain an arm processor (zynq) and three microBlaze processors and I am sending data from arm to a microBlaze and I want to measure the time that the data take to be received at the microBlaze, I connected the arm to AXI timer and I found it in pripheral drivers in SDK but I do not know how to connect the microBlaze, any help?!
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I am trying to accelerate the communication between two FPGA/ARM development boards. Currently, data is passed from RocketCore to the ARM processor to an Ethernet port. This transfer is incredibly slow. Instead, I am trying to connect the RocketCore directly to the development board's peripherals. All documentation I read indicates the only way to get data out of a RocketCore is via MMIO. First is it possible to directly control an FPGA pin via a RocketCore? Second if yes, what command, library etc. would I use?
Functions as simple as would suffice
writePin(pin number, value)
readPin(pin number)
Thank you in advance!
I have tried sending data via the ARM core; however, that is too slow for my application.
I have a device with SPI bus which is connected via PCIe to a linux machine. I'm developing a simple SPI driver for this device. With spi_register_master I can create a SPI master (it is listed under /sys/class/spi_master/spixxxx).
For accessing the bus I would like to use spidev from the userland, but I have not found a way to register a spidev device at runtime. All ways I have found use the device tree to insert the information into the linux kernel.
Is there some way to create spidevdevicesat runtime?
Edit: I suppose it is the same problem with all protocol drivers and not limited to spidev.
I'm looking for a way to send some data from my software app written in C to AXI-Stream interface of Zynq. Something like
open(/dev/axistream);
send_data(data);
I'm running Linux on the Arm part and now I want to connect it to the programmable logic part.
On a zynq device communication between the Cortex-A9 processor and FPGA is done using AXI protocol. There are three types of ports which can be used to communicate between FPGA and CPU (Zynq TRM) :
General Purpose AXI ports: 2x Master (from CPU to FPGA) and 2x Slave port (from FPGA to CPU). these ports are connected to the central interconnect of the processing system and can be used to transfer data to/from DDR memory or on-chip memory (OCM).
High Performance AXI ports: 4x Slave port (from FPGA to CPU) provide high-bandwidith access to DDR or OCM
ACP (Accelerator Coherency Port): Slave port (from FPGA to CPU) high-troughput port connected directly to the snoop control unit (SCU). The SCU maintains cache coherency (ommits the need for cache flush/invalidates).
From your question, I would understand that in your case the CPU is the Master of the communication. You will need to use the General-Purpose axi master ports. You cannot connect an AXI4 streaming interface to the AXI interconnect. You will need to convert AXI4 Streaming to AXI. Depending on your performance needs an AXI DMA ip core (AXI DMA IP core) might be a good solution.
If you want to communicate from software point of view using "open(/dev/)" you will need a Linux device driver. If you are using the DMA core your communication will typically look like this:
You will configure the DMA core to fetch data from a certain memory address
Start the DMA core
the DMA core will fetch the data and feed it to the AXI4 streaming interface of your IP block
Your IP block will do some operation on the data and send back to memory (using DMA) or do something else (send to external interface, ...)
The register set of your DMA core will be memory mapped and accessible through you own linux device driver. For debugging purposes i would suggest using mmap to access the registers and quickly validate the operations of your hardware. Once you go for the linux kernel device driver i would suggest you reading this book: Linux Device Drivers 3the edition
The best choice for efficient data transfer is using DMA enabled PS-PL communication. After implementing a DMA controller inside PL, such as AXI CDMA you can connect it to an AXI4-Stream IP then to your desired IP core.
If your not going to set up a general framework you can access DMA-enabled part of DDR memory using mmap() system call.
Here is a template to transfer data from user space to the IP core in which a loop-back is implemented.
https://github.com/h-nasiri/Zynq-Linux-DMA
Zynq AXI CDMA
The AXI CDMA uses processing system HP slave port to get read/write access of DDR system memory. There is also a Linux OS based application software that uses mmap() to initialize the DMA core and then do the data transfer.
You can easily add an AXI4-Stream interconnect to the AXI CDMA and connect
If I understand correctly, you want to DMA data from the from the PS to PL using the DMA engine. In that case, you would need to write a driver in Linux which will either use the AXI DMA engine driver, or configure the DMA engine from user space.
Is that what you are looking for?
I am working on a project in embedded Linux with beagle bone to transfer 300 bytes of data as one block in one write cycle to a slave (Atmel uC). After having read the Documentation on Spi ie /Documentation/spi I have found that the DMA gets enabled when the data transfer threshold exceeds 160 bytes as mentioned in /drivers/spi/omap2_mcspi.c
I would like to enable flow control based on exchange of const 4 byte values between my beaglebone and Atmel uC. Once I have sent a command say CMD_DATA, the slave responds with RC_RDY. I would like to make a kernel module that services interrupts and calls an interrupt handler every time upon receiving data from slave so that I can check for this ack from slave.
How do I enable interrupts and register interrupt handler for SPI? Any sample codes or tutorials would be helpful. I have looked extensively online and all I found was setting up interrupts for GPIO's
Thanks!
Client/server communication - client is sender and server is receiver.
When the server receives the data on the ethernet interface(UDP) the kernel in the server is triggered. I am using real time LINUX on the server side. Server (i.e. embedded pc target) is handling interrupts to trigger the embedded pc target (containing rt Linux) to gain the attention to execute the newly arrived data.
How can I calculate the time in kernel as soon as the interrupt occurs and send the response back to the client?
1) If you are using an embedded linux platform, you can refer to CPU datasheet: maybe it have a set of high-speed timers. At instance, I'm using SoC based on ARM Cortex A8, it has GP timers that can be clocked up to 38.4 MHz, so I can measure execution time with ~27ns precision. Very likely, your OS would not provide such API, so you're welcome to read-write CPU registers directly from kernel driver.
2) If you are want to just estimate execution time, and nothing more, you can use one of GPIO pins of your board. Set pin up at "start", set down at "end", then watch this pin by oscilloscope, if you have one.
3) If I missunderstood you, and all that you need is timestamp of a real time (like HH:mm:ss), you can refer to RTC chip of your board. Using driver of real-time clock chip, you can read time from your kernel module. Unfortunately, you might not be able do it from interrupt service routine.
Or just call do_gettimeofday and convert timeval to something human-readable via time_to_tm, if needed :)