Uart Module and op - bluetooth

I want to light leds respectively in fpga (Nexys 2 ) by using Verilog, but I didn't synchronize between bluetooth (hc-06) and fpga. For example: I send 255 (1111 1111) from my phone and light led 4. It should have lit all 8 leds.
I doubt that the issue is that I didn't set the baud rate correctly (bluetooth baudrate is default 9600).
My Verilog code is posted below.
Baud rate part :
module baud_rate_gen(input wire clk_50m,
output wire rxclk_en,
output wire txclk_en);
parameter RX_ACC_MAX = 50000000 / (9600 * 10);
parameter TX_ACC_MAX = 50000000 / 9600;
parameter RX_ACC_WIDTH = 9;//$clog2(RX_ACC_MAX);
parameter TX_ACC_WIDTH = 8;//$clog2(TX_ACC_MAX);
reg [RX_ACC_WIDTH - 1:0] rx_acc = 0;
reg [TX_ACC_WIDTH - 1:0] tx_acc = 0;
assign rxclk_en = (rx_acc == 5'd0);
assign txclk_en = (tx_acc == 9'd0);
always #(posedge clk_50m) begin
if (rx_acc == RX_ACC_MAX[RX_ACC_WIDTH - 1:0])
rx_acc <= 0;
else
rx_acc <= rx_acc + 5'b1;
end
always #(posedge clk_50m) begin
if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH - 1:0])
tx_acc <= 0;
else
tx_acc <= tx_acc + 9'b1;
end
endmodule
Transmitter and receiver part is copied from
https://github.com/jamieiles/uart/blob/master/receiver.v
https://github.com/jamieiles/uart/blob/master/transmitter.v
Part of ucf file:
NET "dout<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
NET "dout<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
NET "dout<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
NET "dout<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
NET "dout<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
NET "dout<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
NET "dout<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
NET "dout<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
Pin connectors part:
NET "tX" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
NET "rx" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
uart_top module:
module uart(input wire [7:0] din,
input wire wr_en,
input wire clk_50m,
output wire tx,
output wire tx_busy,
input wire rx,
output wire rdy,
input wire rdy_clr,
output wire [7:0] dout,
output tX,
input reset);
wire rxclk_en, txclk_en;
baud_rate_gen uart_baud(.clk_50m(clk_50m),
.rxclk_en(rxclk_en),
.txclk_en(txclk_en));
transmitter uart_tx(.din(din),
.wr_en(wr_en),
.clk_50m(clk_50m),
.clken(txclk_en),
.tx(tx),
.tx_busy(tx_busy));
receiver uart_rx(.rx(rx),
.rdy(rdy),
.rdy_clr(rdy_clr),
.clk_50m(clk_50m),
.clken(rxclk_en),
.data(dout));
assign tX = 1;
endmodule

First think I noticed is that the receiver has ==15 which suggest a 16x oversampling clock. Looking in github comment section confirms this.
Your baud rate code uses 50000000 / (9600 * 10); which is a 10x baud rate clock, not 16.
In your baud rate code and in git hub UART code there is extensive use of initialized variables. There are many cases where that will not work. The correct way is to use a reset.
I only glanced at the github receiver code but it is very, very sloppy:
No header at the top of the file explaining what it is or does.
Does not have a reset
Has no synchronizer. UART data arrives asynchronous to the clock and needs to be synchronized!
rdy written in two places. Here it means a rdy_clr arriving at the same time as the data byte data losses the data byte.
No overflow detection.
Stop state does not check for bit high. This makes that an unconnected line (always low) is seen as a bit stream of all zeros.
Minor point: Assembling receiving byte is done with a de-multiplexer. scratch[bitpos[2:0]] a lot of slow logic for what you can do with a shift register.

Related

How can I prevent that DSP blocks are synthesized away if they are not connected to a top level output?

I am using an Intel Stratix 10 FPGA and Quartus Prime Pro 21.4 to develop a power test project.
I cannot figure out how keep Quartus from optimizing away my DSP blocks.
I want to use all 3000 DSP blocks in our FPGA so that I can see the max current draw of the DSP block. Of course, we can use the power estimator, but we require a real-world physical test.
I actually don't need the output from the DSP block. I only care that they are running and using FPGA resources.
I have instantiated the Intel fixed DSP core IP as a multiplier:
https://www.intel.com/content/www/us/en/docs/programmable/683450/current/native-fixed-point-dsp-intel-stratix-51840.html
I am using a generate for loop to generate 3000 of these DSP IP blocks. My problem is that the DSP blocks are synthesized away unless I connect the output from each of the DSP blocks directly to a top level output. I only have ~1000 outputs available so this is not possible.
I thought I could just connect each output with a register array to catch the output. But it seems that if I don't actually use the output values or connect it outright to a top level output pin, then Quartus thinks we don't need it and optimizes it away.
The 2nd solution I tried is to use combinational logic:
top_output = DSP_out[0] || DSP_out[1] || DSP_out[2] || DSP_out[3]
this solution will generate 4 DSP blocks even though the generate loop runs 3000 times. I tried doing this in a loop, but it did not work. Is there a way to trick the system into synthesizing all the DSP blocks even if I don't connect the block to a top level output?
I seem to be able to access the output of the DSP block with no issues. For instance, I was able to turn on or off an LED based on the numbers I fed into a single multiplier.
Here is the full code:
`timescale 1ps/1ps
`default_nettype none
module power_test_design (
input wire clk_i,
output reg [0:0] outputa,
output reg [0:0] outputb
);
localparam NUM_DSP_BLOCKS = 3000;
genvar i;
wire reset;
integer k;
//input stimulus signals for the DSP
reg [17:0] ay_r;
reg [17:0] by_r;
reg [17:0] ax_r;
reg [17:0] bx_r;
//create wires and registers to hold outputs from multiplier
(* keep = "true" *) wire [36:0] resulta [NUM_DSP_BLOCKS-1:0];
(* keep = "true" *) reg [36:0] resulta_r [NUM_DSP_BLOCKS-1:0];
(* keep = "true" *) wire [36:0] resultb [NUM_DSP_BLOCKS-1:0];
(* keep = "true" *) reg [36:0] resultb_r [NUM_DSP_BLOCKS-1:0];
reg [2:0] ena_r;
// Stratix10 system reset
reset_release U_RESET (
.ninit_done (reset ) // output, width = 1, ninit_done.ninit_done
);
// DSP stimulus
always #(posedge clk_i) begin : DSP_SET_FF
if (reset)
begin
ay_r <= {18{1'b0}};
by_r <= {18{1'b0}};
ax_r <= {18{1'b0}};
bx_r <= {18{1'b0}};
ena_r <= {3{1'b0}};
end else
begin
ena_r <= 3'b001;
ay_r <= $unsigned(ay_r) + 1;
by_r <= $unsigned(by_r) + 1;
ax_r <= $unsigned(ax_r) + 2;
bx_r <= $unsigned(bx_r) + 3;
end
end
generate
for (i=0; i<NUM_DSP_BLOCKS; i=i+1) begin : GEN_DSPS
dsp_fixed U_DSP (
.ay (ay_r), // input, width = 18, ay.ay
.by (by_r), // input, width = 18, by.by
.ax (ax_r), // input, width = 18, ax.ax
.bx (bx_r), // input, width = 18, bx.bx
.resulta (resulta[i]), // output, width = 37, resulta.resulta
.resultb (resultb[i]), // output, width = 37, resultb.resultb
.clk0 (clk_i), // input, width = 1, clk0.clk
.clk1 (), // input, width = 1, clk1.clk
.clk2 (), // input, width = 1, clk2.clk
.ena (ena_r) // input, width = 3, ena.ena
);
//bring result to a register to assign output logic
assign resulta_r[i] = resulta[i];
assign resultb_r[i] = resultb[i];
end
endgenerate
//output logic -this code generates 6 DSP blocks....I need to generate all 3000
always #(posedge clk_i) begin : outputLogic
for (k=1; k<50; k=k+1)
begin
outputa = resulta_r[k] || resulta_r[k+1] || resulta_r[k+2];
outputb = resultb_r[k+3] || resultb_r[k+4] || resultb_r[k+5];
end
end
endmodule
`resetall
So far, I tried several ways to assign this output. first:
always #(resulta_r[0], resulta_r[1], resulta_r[2], resulta_r[3]) begin
if (resulta_r[0] == 4)
begin
outputa = 1;
end
else if (resulta_r[1] == 6)
begin
outputa = 1;
end
else if (resulta_r[2] == 6)
begin
outputa = 1;
end
else if (resulta_r[3] == 6)
begin
outputa = 1;
end
else
begin
outputa = 0;
end
end
With this code, DSP blocks are generated for each if statement. So, the next idea was
always #(posedge clk_i) begin : outputLogic
for (k=1; k<50; k=k+1)
begin
outputa = resulta_r[k] || resulta_r[k+1] || resulta_r[k+2];
outputb = resultb_r[k+3] || resultb_r[k+4] || resultb_r[k+5];
end
end
This works in a similar way. I get a DSP block generated for each result[k] in the combinational statement. But this only generates 6 DSP blocks in total when synthesizing. It only generates blocks based on how many DSP block outputs are in this combinational statement.
I solved this issue using Virtual pins in quartus. I can assign each output pin to only be a virtual pin and not an actual pin. With this setup I can have as many output pins as I require and not really connect them to anything.
Quartus Virtual Pins
The design still doesn't scale up to 3000 for some reason, but I have reached out to Intel for that. The original issue of optimizing away the DSP blocks unless they are connected to an output is solved.
The other solution that solved this issue was to chain several of these DSP blocks together. It also doesn't scale, but solves the original question asked here as well.

Is there a way I can use an input to determine the clock period?

This program needs to be able to output a sinewave to the testbench, where the frequency of the output signal should be specified by an eight bit
input. My understnading is that I need to change the clock period which will alter the frequency of the waveform accordingly.The code is provided below:
module functionGenerator(Clk,data_out, freq);
//declare input and output
input [7:0] freq;
input Clk;
output [9:0] data_out;
//declare the sine ROM - 30 registers each 8 bit wide.
reg [9:0] sine [0:99];
//Internal signals
integer i;
reg [9:0] data_out;
//Initialize the sine rom with samples.
initial begin
i = 0;
sine[0] = 0; sine[1] = 10; sine[2] = 20; sine[3] = 29; sine[4] = 39;
sine[5] = 48; sine[6] = 58; sine[7] = 67; sine[8] = 75; sine[9] = 84;
sine[10] = 92; sine[11] = 100; sine[12] = 107; sine[13] = 114; sine[14] = 120;
sine[15] = 126; sine[16] = 132; sine[17] = 137; sine[18] = 141; sine[19] = 145;
sine[20] = 149; sine[21] = 151; sine[22] = 153; sine[23] = 155; sine[24] = 156;
sine[25] = 156; sine[26] = 156; sine[27] = 155; sine[28] = 153; sine[29] = 151;
sine[30] = 149; sine[31] = 145; sine[32] = 141; sine[33] = 137; sine[34] = 132;
sine[35] = 126; sine[36] = 120; sine[37] = 114; sine[38] = 107; sine[39] = 100;
sine[40] = 92; sine[41] = 84; sine[42] = 75; sine[43] = 67; sine[44] = 58;
sine[45] = 48; sine[46] = 39; sine[47] = 29; sine[48] = 20; sine[49] = 10;
sine[50] = 0; sine[51] = -10; sine[52] = -20; sine[53] = -29; sine[54] = -39;
sine[55] = -48; sine[56] = -58; sine[57] = -67; sine[58] = -75; sine[59] = -84;
sine[60] = -92; sine[61] = -100; sine[62] = -107; sine[63] = -114; sine[64] = -120;
sine[65] = -126; sine[66] = -132; sine[67] = -137; sine[68] = -141; sine[69] = -145;
sine[70] = -149; sine[71] = -151; sine[72] = -153; sine[73] = -155; sine[74] = -156;
sine[75] = -156; sine[76] = -156; sine[77] = -155; sine[78] = -153; sine[79] = -151;
sine[80] = -149; sine[81] = -145; sine[82] = -141; sine[83] = -137; sine[84] = -132;
sine[85] = -126; sine[86] = -120; sine[87] = -114; sine[88] = -107; sine[89] = -100;
sine[90] = -92; sine[91] = -84; sine[92] = -75; sine[93] = -67; sine[94] = -58;
sine[95] = -48; sine[96] = -39; sine[97] = -29; sine[98] = -20; sine[99] = -10;
end
//At every positive edge of the clock, output a sine wave sample.
always# (posedge(Clk))
begin
data_out = sine[i];
i = i+ 1;
if(i == 99)
i = 0;
end
endmodule
Testbench
module functionGeneratror_tb();
// Inputs
reg Clk;
reg freq;
// Outputs
wire [9:0] data_out;
// Instantiate the Unit Under Test (UUT)
functionGenerator uut (
.Clk(Clk),
.data_out(data_out),
.freq(freq)
);
//Generate a clock with 10 ns clock period.
initial Clk = 0;
always #5 Clk = ~Clk; // CAN I PASS IN AN INPUT HERE INSTEAD OF 5?
initial
#10000 $finish;
endmodule
always #5 Clk = ~Clk;
This statement is part of your testbench, not part of the UUT. You aren't supposed to change it; the expectation is that the clock frequency remains constant.
Your functionGenerator module currently doesn't make any use of the freq input. You will need to come up with some way to control how quickly the synthesizer steps through the sine array based on the value of freq. This may involve either making less than one step per clk period, or making multiple steps per period, depending on your requirements.
This is a typical case in which a phase-acummulator oscillator is used to generate the ROM address for the new sample to output.
Something like this: the phase accumulator here is 14 bits wide, and we are using the 6 most significant bits to have a sine wave of 64 samples. The output frequency of such sine wave is CLK * freq / 16384
Actually, the ROM has only 16 cells, as it needs only to store one quarter of a sine wave. Bits 3 to 0 from the calculated address from the phase accumulator are used to address the ROM, and bits 5 to 4 are used to find out which quadrant we are in, so the actual address may need to be inverted and/or the actual output may need to be negated.
module FunctionGenerator (
input wire clk,
input wire [7:0] freq, // frequency of output signal is: clk * freq / 16384
output reg signed [9:0] out
);
reg signed [9:0] quartersin[0:15];
// Generate initial values with this little C program:
// #include <stdio.h>
// #include <math.h>
//
// #define PI 3.141592654
//
// int main()
// {
// int i;
//
// for (i=0;i<16;i++)
// {
// printf (" quartersin[%2d] = %d;\n", i, (int)(511*sin(i*2*PI/64.0)));
// }
//
// return 0;
// }
initial begin
quartersin[ 0] = 0;
quartersin[ 1] = 50;
quartersin[ 2] = 99;
quartersin[ 3] = 148;
quartersin[ 4] = 195;
quartersin[ 5] = 240;
quartersin[ 6] = 283;
quartersin[ 7] = 324;
quartersin[ 8] = 361;
quartersin[ 9] = 395;
quartersin[10] = 424;
quartersin[11] = 450;
quartersin[12] = 472;
quartersin[13] = 488;
quartersin[14] = 501;
quartersin[15] = 508;
end
reg [13:0] phaseacum = 14'h0000;
reg [3:0] indx;
always #(posedge clk) begin
phaseacum <= phaseacum + {6'b000000, freq};
if (phaseacum[13] == 1'b0) // if in quadrants 0 or 1, out as is
out <= quartersin[indx];
else
out <= -quartersin[indx]; // if in quadrants 2 or 3, negate out
end
always #* begin
if (phaseacum[12] == 1'b0) // which quadrant am I ?
indx = phaseacum[11:8]; // if in quadrant 0 or 2
else
indx = ~phaseacum[11:8]; // else, in quadrant 1 or 3
endcase
end
endmodule
A minimal testbench can be used to let this function generator to run for a thousand or so clock cycles, and then take the output to GTKWave and display it as an analog output:
`timescale 1ns / 1ns
module tb;
reg clk;
reg [7:0] freq;
wire [9:0] out;
FunctionGenerator uut (
.clk(clk),
.freq(freq),
.out(out)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1,uut);
clk = 1'b0;
freq = 8'd16; // aprox. 1 kHz sine wave for a 1 MHz clk
repeat (2000) begin
#(posedge clk);
end
$finish;
end
always begin
clk = #500 ~clk; // a 1 MHz clock
end
endmodule
This is the result, simulated with iverilog / GTKWave:

Why can't I connect a register to an output in Verilog?

I am trying to teach myself FPGA's using a Nexsys 2 design lab (Spartan 3E 1200 FPGA) and Xilinx 12.4. I've been able to get most basic functions to work, but I can't seem to modify a register in an always block then assign an output to it. Here is my stripped-down code for a blinking LED.
`timescale 1ns / 1ps
`define MHZ 33000
module VerilogFirst(
input clk,
output led5
);
reg myout = 1'b0;
reg[0:8] timer = 8'b00000000;
always #(posedge clk) begin
if (timer >= `MHZ) begin
myout <= ~myout;
timer <= 0;
end
else begin
myout <= myout;
timer <= timer + 1;
end
end
assign led5 = myout;
endmodule
And the UCF:
NET "clk" LOC = "B8";# Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
NET "led5" LOC = "P15";# Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
Everything works fine, but when I try to generate the bitstream, I get an error stating that the LED isn't connected to anything.
ERROR:PhysDesignRules:368 - The signal <led5_OBUF> is incomplete. The signal is not driven by any source pin in the design.
ERROR:PhysDesignRules:10 - The network <led5_OBUF> is completely unrouted.
ERROR:Bitgen:25 - DRC detected 2 errors and 1 warnings. Please see the previously displayed individual error or warning messages for more details.
The constant MHZ of 33000 won't fit into 9-bit register timer.
So timer can never exceed that value, myout will never flip. The timer value is also never used, because its value can't affect anything, so the compiler will optimize away everything, entirely. Even clk signal will be left unused, and you will get a warning about that.

error when elaborating in design vision

I am trying to write a code in verilog and synthes it in design vision but when elaborating design vision give below errors :
net "countS[5]" is driven by more than one source,and at least one source is constant net
net "countS[4]" is driven by more than one source,and at least one source is constant net
net "countS[3]" is driven by more than one source,and at least one source is constant net
net "countS[2]" is driven by more than one source,and at least one source is constant net
net "countS[1]" is driven by more than one source,and at least one source is constant net
net "countS[0]" is driven by more than one source,and at least one source is constant net
net "countH[5]" is driven by more than one source,and at least one source is constant net
net "countH[4]" is driven by more than one source,and at least one source is constant net
net "countH[3]" is driven by more than one source,and at least one source is constant net
net "countH[2]" is driven by more than one source,and at least one source is constant net
net "countH[1]" is driven by more than one source,and at least one source is constant net
net "countH[0]" is driven by more than one source,and at least one source is constant net
my code exist in below :
module main(clk,ts1,ts2,ts3,ts4,mode,res);
//clock of circuit
input clk;
//input switchs that indicate delays in test mode
input [3:0] ts1;
input [3:0] ts2;
input [3:0] ts3;
input [3:0] ts4;
//input switch that indicate mode of circuit
input [1:0] mode;
//output that indicate state of circuit
output reg [2:0] res;
//regs for counting
reg [5:0] countH;
reg [5:0] countS;
//array that indicate delays
reg [7:0] delays [3:0];
initial begin
//resetting circuit variables
countH = 0;
countS = 0;
res = 0;
//setting delays for regular mode
delays[0] = 30; //rg
delays[1] = 5; //ry
delays[2] = 45; //gr
delays[3] = 5; //yr
end
//trig always whenever mode was changed
always #(mode[0] or mode[1]) begin
//restarting timer
countH = 0;
countS = 0;
//mean that mode is regular
if(mode == 2'b00) begin
delays[0] = 30; //rg
delays[1] = 5; //ry
delays[2] = 45; //gr
delays[3] = 5; //yr
//mean that mode is test mode
end else if(mode == 2'b01) begin
//setting delays according to input switchs
delays[0] = ts1; //rg
delays[1] = ts2; //ry
delays[2] = ts3; //gr
delays[3] = ts4; //yr
//mean that mode is standby
end else begin
delays[0] = 0; //rg
delays[1] = 0; //ry
delays[2] = 0; //gr
delays[3] = 0; //yr
res = 4;
end
end
//trig in all clocks
always #(negedge clk) begin
countH = countH + 1;
//count=60 mean 1sec
if(countH == 60) begin
//updating variables
countH = 0;
countS = countS + 1;
//mean that mode is standby
if(mode == 2) begin
res = 4;
countS = 0;
//mean that mode is regular or test
end else begin
//checking for delay
if(countS == delays[res]) begin
countS = 0;
res = res + 1;
if(res == 4) begin
res = 0;
end
end
end
end
end
endmodule
The errors are generated by the synthesis tool, since synthesis tries to convert the design written i Verilog to hardware, but during this translation it finds that the wires countS (and other) are driven from several locations.
These locations are the initial and always blocks where the wires are assigned. Think of it like doing a design using discrete gates; in this case it would also lead to a problem if multiple drive the same wires.
So you need to modify the design, so each wire/reg is only driven by one always block or continuous assignment, where the initial block is probably to be converted to some asynchronous or synchronous reset, or initial value like reg [5:0] countS := 0;.

Verilog Xilinx - FPGA board - Cannot instantiate three multiple instances of counting module

I want to instantiate 3 instances of my counter module. However, Xilinx will only instantiate one counter for me, not the three. Does anyone know why this is? In the RTL schematic, the 2nd two counters are connected straight to ground in their block diagrams, i.e. no logic implemented for them. Are my local parameters declared correctly?
I would really really appreciate your help. I have been staring at this problem for several hours.
Thank you so much for your help. It is really appreciated.
//Top Level Module:
`timescale 1ns / 1ps
//Top Level Wrapper module
module topWrapper(input CCLK, input reset, output clk, output max_tick_Green, output max_tick_Red, output max_tick_Amber);
localparam
M_Green = 5;
M_Red = 3;
M_Amber = 2;
//Frequency scaling of CCLK
//clk is used in the traffic light module and is a scaled version of CCLK
//CCLK: Frequency = 50MHz, Period = 20ns
//clk = Frequency = 1Hz, Period = 1s
//clkscale (frequency scaling parameter) = 1s/20ns = 5x10^7
clock clockScalingModule (CCLK, 50000000, clk);
//Counter for green light
//In traffic light sequence, change from green to amber after 12 clock cycles = 120s = 2mins
counter #(.M(M_Green)) countGreen
(.clk(clk), .reset(reset), .state(1), .max_tick(max_tick_Green));
//Counter for red light
//In traffic light sequence, change from green to amber after 12 clock cycles = 120s = 2mins
counter #(.M(M_Red)) countRed
(.clk(clk), .reset(reset), .state(1), .max_tick(max_tick_Red));
//Counter for amber light
//In traffic light sequence, change from green to amber after 12 clock cycles = 120s = 2mins
counter #(.M(M_Amber)) countAmber
(.clk(clk), .reset(reset), .state(1), .max_tick(max_tick_Amber));
endmodule
//Counter module:
//Counter - modulo M counter - counts 0 to M-1, then wraps around
module counter
//Parameters
//M = number of clock cycles the counter counts = max value
#(parameter M = 6)
//I/O signals
(
input wire clk, reset, state,
output wire max_tick
);
//Local parameter
//N = number of bits in counter
//N = ceiling(log2(M)) - definition at end of module
localparam N = clog2(M);
//Internal signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
//Body
//Rgister update
always#(posedge clk, posedge reset)
//Restart counter if reset is High or state is Low
//State = Low if this counter's light is not currently on
//State = High if this counter's light is currently on
if(reset)
r_reg <= 0;
//Only increment counter if state is High
//Only one of red, green, amber states is high
else if(state)
r_reg <= r_next;
else
r_reg <= 0;
//Next-state logic
assign r_next = (r_reg == M) ? 0: r_reg + 1;
//Output logic
//Max tick = HI when maximum count value is reached
//Max tick = LO otherwise
assign max_tick = (r_reg == M) ? 1'b1 : 1'b0;
//Ceiling log2() function definition
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
endmodule
Your issue is in your counter module. Your clog2 function returns the number of bits needed to represent inputvalue-1. Thus, if inputvalue is exactly a power of two, you can't represent inputvalue with the returned length.
This is probably not very clear, so let's look at what happens for M_amber = 2. In this case, clog2 return 1, r_reg is range [0:0], but you need 2 bits to represent 2 = 2'b10. And you need to be able to represent 2, since you have the checks r_reg == M in your code. Said check will always fail, and Xilinx remove the logic and connects your logic to ground.
Normally, if you want to count N cycles in HDL, you count from 0 to N-1. Thus, your code will be fine if you replace r_reg == M for r_reg == M-1.

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