This is the issue. For the schematic, please refer to the schematic attached. I have a pins component with a set of pins. I need to access each pin at a time. Currently I am trying to do that with the code,
DisplayEnable_0_Write(1);
DisplayEnable[0]_Write(1);
DisplayEnable_Write(1);
All of them refuse to work. How can I do this?
the schematic diagram
First thing to note is it doesn't look like you have any of the PSoC pins assigned other than 1[7] (Note how all the others are marked with an [X]). You should assign the other pins in the design wide resources file (.cydwr) otherwise the fitter will automatically assign them wherever it pleases (I think it just chooses the first available?).
[EDIT] My mistake, the pins will be marked with [X] if they are not continuous.
Individual pins in a component can be written by using the macros generated in the Pin_aliases.h file (see page 36 of the pins component datasheet). In your case this would be DisplayEnable_aliases.h. So in your example, you would set the pin in position 0 by:
CyPins_Set(DisplayEnable_0);
Clear the pin via:
CyPins_Clear(DisplayEnable_0);
Related
I am trying to write a custom syscall handler that manipulates the LEDs on a BeagleBone Black board. I have gone through the kernel LED API (include/leds.h), but I am unable to find anything that'd give me a handle to the available LED devices or some other mechanism to manipulate (on/off/toggle) them. Most of the functions seem to require a led_classdev object, but I can't find a way of getting one.
I can do this from userspace using the /sys/class/leds/... interface. But I want to do something similar from kernel space. I am open to hard-coding any device names specific to BeagleBone Black as portability is not an issue.
I figured out a way to access/control the LEDs from kernel space - by creating a custom LED trigger. It doesn't give a way to enumerate available devices, and it requires the custom trigger to be assigned for an LED from user-space by writing to /sys/class/leds/foo/trigger. But it lets you manipulate the LEDs from kernel code once the trigger is assigned.
struct led_trigger *trigger;
...
led_trigger_register_simple("myled", &trigger); //create and register the trigger
...
//assign the trigger "myled" to the desired LED(s) from user-space
//by writing to the corresponding trigger files in /sys/class/leds/foo/
...
led_trigger_event(trigger, LED_FULL); //turn-on the LED(s) connected to the trigger
led_trigger_event(trigger, LED_OFF); //turn-off
The creation and registering of trigger can be done in a module init, for example. Also, if one needs to manipulate multiple LEDs independently, then as far as I can see, one needs to create separate triggers for each LED.
An interesting issue arose with a device whose SWD_CLK pin is shared as a 'device boot mode' pin (ROM/Flash boot, etc.). The specification states that the SWD_CLK should be held high for some time before functioning as SWD_CLK.
The origen_swd plugin drives the clock high to 'enable' it, so the timeset for this pin must be 'return low' in order to clock. But, when I try to drive this high and hold it high, it begins clocking. Is there a way to disable the timeset for some time, then re-enable it when ready?
The workaround is to change the origen_swd to accept an option to either drive high or drive low to enable, then change the timeset in my application to return high.
Using metaprogramming to just grab and edit instance variables of the timeset may also be a solution, but is there a supported API to handle the tasks like the above?
Thanks
The way to do this would be by making two timing options for the given pin, one with the return low and one without.
tester.set_timeset "mode_entry", 40
pin(:swd_clk).drive!(1)
# Sometime later once in mode
tester.set_timeset "func_swd", 40
If the tester supports (e.g. V93K) you can also define multiple wave forms for a pin within the same timeset, as shown at the end of this guide section - http://origen-sdk.org/origen/guides/pattern/timing/#Complex_Timing
Then you would just have a single timeset selection and control the wave you want on the pin like this:
pin(:swd_clk).drive!(1) # Would be defined in the timing as always high
pin(:swd_clk).drive!('P') # Now start the clk pulse
Both of these approaches will work in the generated ATE patterns, however at the time of writing I believe that OrigenSim does not yet support the second approach, so you will have to use the multiple timesets.
As an aside, you sound like you are only looking for a solution that works in simulation and not necessarily required to have the two types of waves within the final ATE pattern.
In that case, you could also try poking the testbench's pin driver force data bit, though I haven't tried this:
tester.simulator.poke('origen.pins.swd_clk.force_data[1]', 1);
If you have success with that, we should think about adding a convenience API to do this kind of thing in simulation:
pin(:swd_clk).force!(1)
I have a raspberry pi, I want to use one single pwm channel to control a rgb led. There are 2 pins available for pwm0. So I connected red led on first pin and green led on second pin. I connected the blue one on a gpio. When I enable pwm0, the red and green leds are on. I would like to control them individually. I know it will be same period and duty cycle but is there a way to turn one pin off without disabling the entire pwm channel ?
You need to provide more information, such as a code snippet, the library you are using and the schematic. You can find more information on this specific stackexchange thread for raspberry: PWM on Raspberry. You must be having trouble configuring your pins. For sure, you are able to do it.
I have an (Adafruit Feather Huzzah) ESP2866 WiFi module which has an (EN) pin to disable the 3v3 output on the chip. This pin is pulled up by default and normally you would just connect it to GND in order to switch off the 3v3 regulator (and disable the peripherals).
What I am trying to achieve is that when the ESP2866 is in "Deep Sleep" mode that the 3v3 output is disabled. Ideally if there was a pin that was pulled down by default when the device is asleep then I could just hook that into (EN) pin but I don't think this exists. However, there are pins that are pulled high by default when the device is fully awake.
What I was considering doing was using a high value resistor to create a weak pull down on this pin by using this to join GND to (EN). Then I would also directly join another pin that is pulled up when the module is on to "cancel out" the pull down. I have a feeling that I might need to end up using a transistor (or a few components) to toggle this low.
Reading the Adafruit forums I have since discovered that pulling the EN pin also switches off the ESP2866 internal circuitry so it will never come back out of deep sleep. On this basis there is no solution to this specific question as there will never be a high pin (without some form of external circuitry).
Thanks to those who bothered to read.
I'm using a Virtex 5 FPGA and want to have a few +5/0 I/O pins to communicate with a microcontroller. The only peripherials I've used on the board so far are pushbuttons and switches and no one I've asked seems to know the simplest way to do this I/O. I've looked around the board specification but haven't found any simple way of doing it. I would appreciate any advice you might have.
This is not an easy thing to do. If you don't have the schematic of the board, then you need to get volt meter with some fine pitch probes and reverse engineer the board.
It is pretty easy if you have 2 boards, with one board it can be really hard since the BGA signals may not be connected to a via and therefore not available on the bottom of the board, and even if they are, then you don't know exactly which pin they are connected to. But with some luck, you can find them since the VIA can only be connected to 4 possible pins surrounding it!
The first thing you need to do is to identify your chip, find the BGA print of the IC from Xilin'x web site.
If your board has some buttons already, then if you are lucky, those signals may be routed to the pins of the FPGA that are available on the bottom of your board. Here are the things you need to do:
Make sure you have good ESD protection to perform these test
Put your voltmeter into 'buzzer' mode
Check the pins of your connector and find out how it is connected, see if there is a pull-up and/or pull-down resistors on the board
when you find the 'active' pin of your connector, start connecting the other probe to the VIAs one by one
When you hear a buzz, make a note of the position (guess or measure the distance between the side of t he IC and the location of the via)
Identify the 4 possible pins that the signal can be connected to
Write a code to get all those 4 signals and connect them to ChipScope
In Chip Scope, capture all 4 signals and see which one is the one with the right connection!
alternative, you can create a design with inputs only, capture all the inputs and put them into a memory block and create a trigger logic to capture all the signals whenever any of the inputs changes, after lots of work and analysis, you will find the correct pins.
Anyway, these are just crazy ideas since this is a really difficult thing to do without having the PCB info of the board.
Good luck with your hacking.