Giving a matrix as an input to a verilog module - verilog

Question

I am working with the implementation of a Product Code on FPGA . The product code is basically a matrix with the rows and columns being codewords coming from a BCH codebase (BCH(1023,993,3)) . I already have a BCH decoder in Verilog . I want to have a 1023 by 1023 matrix as an input to my Product code decoder and then call upon that module to decode the rows and columns of the product code matrix . The way the decoding process works at a higher level is that , if there are more than 3 errors in a codeword , the BCH decoder module fixes those errors and moves to the next row/ column .
The questions I have are as follows :
1) Is it possible to make the input port as a matrix ?
2) If I need to pipeline the decoding process, do I need to instantiate the BCH decoder 1023 times or is there a better way to do it ?
3) If it is not possible to make the input port as a matrix , do I need to give all the 1023 rows as 1-D vectors like input row1[1022:0] or is there a better way to do that ?
4) If the technique mentioned in step 3 is the only one available, how do I make the column vectors out of those row vectors available as the inputs ?
Thanks in advance. I really appreciate your time and effort .

Answer 1

One can not pass a two dimensional array as a port in Verilog. SystemVerilog supports 2D array as ports of modules.
Here, you need to take a vector and do some pack/unpack operations. One can define macros for the same.
Here is a sample code where PACK_ARRAY macro packs two dimensional array into a single vector. Packing is done based on the width and length provided as input. Similarly, UNPACK_ARRAY unpacks a vector into a two dimensional array.
`define PACK_ARRAY(PK_WIDTH,PK_LEN,PK_SRC,PK_DEST) \
genvar pk_idx; \
generate \
for (pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) \
begin \
assign PK_DEST[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)] = PK_SRC[pk_idx][((PK_WIDTH)-1):0]; \
end \
endgenerate
`define UNPACK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC) \
genvar unpk_idx; \
generate \
for (unpk_idx=0; unpk_idx<(PK_LEN); unpk_idx=unpk_idx+1) begin \
assign PK_DEST[unpk_idx][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*unpk_idx+(PK_WIDTH-1)):((PK_WIDTH)*unpk_idx)]; \
end \
endgenerate
module example (
input [(63):0] pack_4_16_in,
output [(31):0] pack_16_2_out
);
wire [3:0] in [0:15];
`UNPACK_ARRAY(4,16,in,pack_4_16_in)
wire [15:0] out [0:1];
`PACK_ARRAY(16,2,in,pack_16_2_out)
// useful code goes here
endmodule // example
As suggested in comments, I believe that you should think of some other approach rather than directly providing 1023*1023 wires as input and output to a single module. As an alternative, you can provide the 1023*1023 matrix elements row wise and store them into internal memory of module.
module example(
input [1023:0] inp, // One can take 'load', 'addr' etc as inputs also
input clk, rst,
output [1023:0] out
);
reg [1023:0] mem [0:1023];
reg [9:0] cnt;
always #(posedge clk) begin
mem[cnt] <= inp;
cnt <= cnt + 1;
end
// Some other logic
endmodule
Here, it will take 1K clocks to load the memory and some glue logic might be required. But this approach will implement a memory inside the module and you will not have hard coded million wires coming as ports.
Refer to this forum discussion for the above code.