I have been giving a specification to derive 10MHz,5MHz and 1MHz from a 20MHz system clock. I am also supposed to design posedge and negedge flags for all the three derived clocks.
I used a 4 bit counter which counted from 0-15 and the counter[0] gave me the 10MHz clock signal and the counter [1] gave me the 5MHz signal. I used another 5 bit counter which counted from 0-9. I made my 1MHz signal register toggle for 0-9 each count, which gave me the 1MHz clock signal.
Now I am struggling to design the posedge and negedge flags for all three of the clocks. I used a combination logic of posedge = a^!b; but I could get the flags for 10MHz and 5MHz but couldn't extract my 1MHz flags from this method.
I was suggested to use my two counters (4 bit and 5 bit) to easily design the flags for all three of them. Kindly suggest on this
my 1MHz snippet using the 5 bit counter
if(counter_1MHz == 5'd9)
begin
counter_1MHz <= 5'd0;
clk_1MHz_reg <= ~clk_1MHz_reg;
end
else
begin
counter_1MHz <= counter_1MHz + 5'd1;
clk_1MHz_reg <= clk_1MHz_reg;
end
assign clk_1MHz = clk_1MHz_reg;
posedge = a&!b where b is one cycle delayed from a:
always #(posedge clock)
b <= a;
assign rising_edge = a & !b; // a is high but was low
Beware that a posedge from a 10 MHz clock derived from a 20MHz clock, is the 10MHz clock again. The negedge is the inverse clock. As such the requirement for those signals seems not very much thought out.
Building on your code:
reg clk_1MHz_delay;
wire clk_1MHz_rising;
always#(posedge clk_20MHz)
clk_1MHz_delay <= clk_1MHz;
assign clk_1MHz_rising = clk_1MHz & !clk_1MHz_delay;
Related
I have 2 clocks, fast clock and slow clock. I am trying to make a clock pulse trigger by the rising edge of the slow clock, with duration of 1 fast clock cycle. I have managed to create similar as shown, but this is using an arbitrary counter, and I need to guarantee it will happen on the rising edge of the slow clock.
Ideas appreciated.
module clock_check;
reg clk18M = 1'b0;
always #1 clk18M <= ~clk18M;
wire clk6M;
wire clk_puls;
reg [4:0] clk18div = 5'b00000;
always #( posedge clk18M ) clk18div <= clk18div+5'd1;
assign clk6M = clk18div[4];
assign clk_puls = clk18div[4:0]==5'b10000;
initial
begin
#200;
$finish();
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
I think this will do what you need.
It has two outputs, choose which one is best suited for your need.
Output LED1 is optimised to keep the latency and jitter of the rising edge as low as possible.
The other output sacrifices latency and jitter for keeping the pulse width constant.
I don't think there is a way that can guarantee both low latency and constant pulse width.
This of course is assuming your two clock signals are not synchronised. If they are then that problem goes away.
It will cope with variations in frequency of the clocks as there is nothing like the arbitrary counter you wanted to get rid of.
With some small modifications you can change the pulse with between being equal to the period of the fast clock or half of it.
The PLL in the code is just a stand in for the clock signals you have, which I'm assuming are some external signal.
Here I deliberately made the two clocks not be exact multiples so I would have a different delay between the rising edges on each cycle to set a worst case scenario.
For that reason I set the two clocks at 25MHz and 2.4MHz respectively.
The 400MHz clock is just for the SignalTap analyzer, to give it a much higher sampling rate than the signals it is recording.
module Cyclone5FirstTest
(
input clk50MHz,
output LED1,
output LED2,
output fClock,
output sClock,
output refClock
);
reg prevState1;
reg prevState2;
reg pulseOut;
wire fastClock;
wire slowClock;
assign fClock = fastClock;
assign sClock = slowClock;
assign LED1 = ( sClock==1 && prevState1==0 );
assign LED2 = ( prevState1==1 && prevState2==0);
PLL_1 PLL_1
(
.refclk (clk50MHz),
.outclk_0 (fastClock), // 25MHz
.outclk_1 (slowClock), // 2.4MHz
.outclk_2 (refClock) // 400 MHz - clock for logic analyzer
);
always #(posedge fastClock)
begin
if ( slowClock & !prevState2 ) pulseOut <= 1;
else pulseOut <= 0;
prevState1 <= slowClock;
prevState2 <= prevState1;
end
endmodule
SignalTap trace
I am absolute beginner in Verilog and I am wondering how does the addition statement work in this piece of program.
reg [7:0] hcount;
...
always #(posedge clk) begin
if(!n_rst) begin
hcount <= 'd0;
end else if(hcount== (WIDTH-1)) begin
hcount <= 'd0;
end else begin
hcount <= hcount + 1'b1;
end
end
I understand that 1'b1 expands to 8'b1 because hcount has 8 bit width and now the calculation will work with 8 bit now. But how exactly does that addition work? Your help is much appreciated.
Verilog is a hardware description langue in a sense that it tries to describe behavior of real hardware. One of attributes of modern hardware is clock. Clock drives flops which synchronize data across different hardware devices.
Clock behavior in verilog is simulated by posedge clk (or negede), meaning that the corresponding always block will be executed if and only if clk switches to 1 from any other value (x, z, 0);.
So, in your case, there is supposed to be a clock (clk) which gets generated somewhere in test bench. It periodically switches between 0 and 1.
As soon as it switches 0 -> 1 it gets executed. If condition is right, the hcount <= hcount + 1'b1 will be executed. As you mentioned the compiler will zero-extend 1'b1 to the 8-bit value 00000001. The rest is the same as in any programming language, hcount will be incremented.
There is certain semantic associated with the non-blocking assignment, <=, but this would be a different question. For the purpose of your question it does not matter.
So, a result will be that a single increment will be done every clock cycle unless n_rst is '0'. Also, as soon as the counter reaches WIDH - 1 it will be set to '0'. Only one operation is allowed at a single clock edge.
I'm trying to write a RTL model in which I monitor independent clock sources. These clock sources can have variable frequency (range 5 to 50MHz)
Let us say clk1 and clk2. I'm trying to drive a signal 'toggle' which is set '1' at every posedge of clk1 and is set to '0' at every negedge of clk2. I'm having trouble realizing this model.
I tried using 1 flop triggered at the positive edge of clk1 with inputs of this flop tied to 'high' and another flip flop triggered at the negative edge of clk2 with input tied to 'low'. I sent these outputs to a mux, but I have trouble figuring out how to drive the select signal of this mux
Here is my code snippet :
always_ff #(posedge clk1 or rstb) begin
if(!rstb) begin
flop1_out <= 0;
end else begin
flop1_out <= 1;
end
end
always_ff #(negedge clk2) begin
flop2_out <= 0;
end
assign toggle = sel ? flop1 : flop2;
So, as of now nothing is driving sel and trying to figure this out is where I'm having trouble
If I try to drive the same signal (toggle) from 2 different clock sources, I get an error saying that multiple drivers found for signal toggle, which makes sense.
Please let me know if you have any suggestions
EDIT: fixed a typo and removed rstb from the sensitivity list for flop2
assign rstn = clk2;
always # (posedge clk1 or negedge rstn)
if (~rstn)
toggle = 1'b0;
else
toggle <= 1'b1;
note: depending on the clock frequency and insertion delay relationships this circuit may become metastable. if you can tolerate delay, add a synchronizer on the output. better yet, if you can tolerate distortion, add a reset synchronizer on clk2 to clk1mx, where clk1mx is synchronous to clock1 but x times faster.
I Want to Design a Verilog code for Interfacing 16*2 LCD. As in LCD's to give "command" or "data" we have to give LCD's Enable pin a "High to low Pulse " pulse that means
**E=1;
Delay();//Must be 450ns wide delay
E=0;**
This the place where I confuse I means in Verilog for synthesis # are not allowed so how can I give delay here I attached my code below. It must be noted that I try give delay in my code but I think delay not work so please help me to get rid of this delay problem......
///////////////////////////////////////////////////////////////////////////////////
////////////////////LCD Interfacing with Xilinx FPGA///////////////////////////////
////////////////////Important code for 16*2/1 LCDs/////////////////////////////////
//////////////////Coder-Shrikant Vaishnav(M.Tech VLSI)/////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
module lcd_fpgashri(output reg [7:0]data,output reg enb,output reg rs,output reg rw ,input CLK);
reg [15:0]hold;
reg [13:0]count=0;
//Code Starts from here like C's Main......
always#(posedge CLK)
begin
count=count+1; //For Delay
//For LCD Initialization
lcd_cmd(8'b00111000);
lcd_cmd(8'b00000001);
lcd_cmd(8'b00000110);
lcd_cmd(8'b00001100);
//This is a String "SHRI" that I want to display
lcd_data(8'b01010011);//S
lcd_data(8'b01001000);//H
lcd_data(8'b01010010);//R
lcd_data(8'b01001001);//I
end
//Task For Command
task lcd_cmd(input reg [7:0]value);
begin
data=value;
rs=1'b0;
rw=1'b0;
enb=1'b1; //sending high to low pulse
hold=count[13]; //This is the place where I try to design delay
enb=1'b0;
end
endtask
//Task for Data
task lcd_data(input reg [7:0]value1);
begin
data=value1;
rs=1'b1;
rw=1'b0;
enb=1'b1; //sending high to low pulse
hold=count[13]; //This is the place where I try to design delay
enb=1'b0;
end
endtask
endmodule
You seem to be stuck in a software programming mindset based on your code, you're going to have to change things around quite a bit if you want to actually describe a controller in HDL.
Unfortunately for you there is no way to just insert an arbitrary delay into a 'routine' like you have written there.
When you write a software program, it is perfectly reasonable to write a program like
doA();
doB();
doC();
Where each line executes one at a time in a sequential fashion. HDL does not work in this way. You need to not think in terms of tasks, and start thinking in terms of clocks and state machines.
Remember that when you have an always block, the entire block executes in parallel on every clock cycle. When you have a statement like this in an always block:
lcd_cmd(8'b00111000);
lcd_cmd(8'b00000001);
lcd_cmd(8'b00000110);
lcd_cmd(8'b00001100);
This does you no good, because all four of these execute simultaneously on positive edge of the clock, and not in a sequential fashion. What you need to do is to create a state machine, such that it advances and performs one action during a clock period.
If I were to try to replicate those four lcd_cmd's in a sequential manner, it might look something like this.
always #(posedge clk)
case(state_f)
`RESET: begin
state_f <= `INIT_STEP_1;
data = 8'b00111000;
end
`INIT_STEP_1: begin
state_f <= `INIT_STEP_2;
data = 8'b00000001;
end
`INIT_STEP_2: begin
state_f <= `INIT_STEP_3;
data = 8'b00000110;
end
`INIT_STEP_3: begin
state_f <= `INIT_STEP_4;
data =8'b00111000;
end
`INIT_STEP_4: begin
state_f <= ???; //go to some new state
data = 8'b00000110;
end
endcase
end
Now with this code you are advancing through four states in four clock cycles, so you can start to see how you might handle writing a sequence of events that advances on each clock cycle.
This answer doesn't get you all of the way, as there is no 'delay' in between these as you wanted. But you could imagine having a state machine where after setting the data you move into a DELAY state, where you could set a counter which counts down enough clock cycles you need to meet your timing requirements before moving into the next state.
The best way to introduce delay is to use a counter as Tim has mentioned.
Find out how many clock cycles you need to wait to obtain the required delay (here 450ns) w.r.t your clock period.
Lets take the number of clock cycles calculated is count. In that case the following piece of code can get you the required delay. You may however need to modify the logic for your purpose.
always # (posedge clk) begin
if (N == count) begin
N <= 0;
E = ~E;
end else begin
N <= N +1;
end
end
Be sure to initialize N and E to zero.
Check the clock frequency of your FPGA board and initialize a counter accordingly. For example, if you want a delay of 1 second on an FPGA board with 50MHz clock frequency, you will have to write a code for a counter that counts from 0 to 49999999. Use the terminalCLK as clk for your design. Delayed clock input will put a delay to your design. The psuedo code for that will be:
module counter(count,terminalCLK,clk)
parameter n = 26, N = 50000000;
input clk;
output reg [n-1:0] count;
output reg terminalCLK;
always#(posedge clk)
begin
count <= count + 1;
if (count <= N/2)
terminalCLK <= ~terminalCLk;
if (count == N)
terminalCLK <= ~terminalCLk;
end
I want to have a 2 sec counter in my for loop such that there is a gap of 2 seconds between every iteration.I am trying to have a shifting LEDR Display
Code:
parameter n =10;
integer i;
always#(*)
begin
for(i=0;i<n;i=i+1)
begin
LEDR[i]=1'b1;
//2 second counter here
end
end
What is your desired functionality? I assume: shifting which LED is on every 2 seconds, keeping all the other LEDs off? "Sliding LED"...
Also, I am assuming your target is an FPGA-type board.
There is no free "wait for X time" in the FPGA world. The key to what you are trying to do it counting clock cycles. You need to know the clock frequency of the clock that you are using for this block. Once you know that, then you can calculate how many clock rising edges you need to count before "an action" needs to be taken.
I recommend two processes. In one, you will watch rising edge of clock, and run a counter of sufficient size, such that it will roll over once every two seconds. Every time your counter is 0, then you set a "flag" for one clock cycle.
The other process will simply watch for the "flag" to occur. When the flag occurs, you shift which LED is turned on, and turn all other LEDs off.
I think this module implements what Josh was describing. This module will create two registers, a counter register (counter_reg) and a shift register (leds_reg). The counter register will increment once per clock cycle until it rolls over. When it rolls over, the "tick" variable will be equal to 1. When this happens, the shift register will rotate by one position to the left.
module led_rotate_2s (
input wire clk,
output wire [N-1:0] leds,
);
parameter N=10; // depends on how many LEDs are on your board
parameter WIDTH=<some integer>; // depends on your clock frequency
localparam TOP=<some integer>; // depends on your clock frequency
reg [WIDTH-1:0] counter_reg = 0, counter_next;
reg [N-1:0] leds_reg = {{N-1{1'b0}}, 1'b1}, leds_next;
wire tick = (counter_reg == 0);
assign leds = leds_reg;
always #* begin : combinational_logic
counter_next = counter_reg + 1'b1;
if (counter_next >= TOP)
counter_next = 0;
leds_next = leds_reg;
if (tick)
leds_next = {leds_reg[N-2:0], leds_reg[N-1]}; // shift register
end
always #(posedge clk) begin : sequential_logic
counter_reg <= counter_next;
leds_reg <= leds_next;
end
endmodule