module lab2_4bit_adder(
input [3:0] A,
inout [3:0] B, //B=Z
input C0,
input [3:0] B1,
input Switch,
inout [3:0] B2,
output [3:0] S,
output C4
);
wire C1;
wire C2;
wire C3;
wire B;
wire B2;
assign B2 = ~B1 + 1'b1;
assign B = (Switch == 0)? B1:B2;
assign B = (Switch == 1)? B2:B1;
assign B = Switch? B2:B1;
lab2_1bit_adder fa0(A[0], B[0], C0, S[0], C1);
lab2_1bit_adder fa1(A[1], B[1], C1, S[1], C2);
lab2_1bit_adder fa2(A[2], B[2], C2, S[2], C3);
lab2_1bit_adder fa3(A[3], B[3], C3, S[3], C4);
endmodule
the error shows:
cannot index into non-array B
please help me to solve it
thank you very much
What you have done is re-declared the variable B as a wire which is not an array. Its a simple wire variable.
So when you are trying to access B[0] in this piece of code it is generating an error and saying that B is not an array and so you cannot index it. Just remove the re-declarations the code will work fine.
lab2_1bit_adder fa0(A[0], B[0], C0, S[0], C1);
lab2_1bit_adder fa1(A[1], B[1], C1, S[1], C2);
lab2_1bit_adder fa2(A[2], B[2], C2, S[2], C3);
lab2_1bit_adder fa3(A[3], B[3], C3, S[3], C4);
Also somehow re-declarations were probably allowed in older versions of Verilog as per this question. But no one has clarified it yet in the answer, but you can check the discussion board.
Final code should look like:
module lab2_4bit_adder(
input [3:0] A,
inout [3:0] B, //B=Z
input C0,
input [3:0] B1,
input Switch,
inout [3:0] B2,
output [3:0] S,
output C4
);
wire C1;
wire C2;
wire C3; //removed all redeclarations
assign B2 = ~B1 + 1'b1;
assign B = (Switch == 0)? B1:B2;
assign B = (Switch == 1)? B2:B1;
assign B = Switch? B2:B1;
lab2_1bit_adder fa0(A[0], B[0], C0, S[0], C1);
lab2_1bit_adder fa1(A[1], B[1], C1, S[1], C2);
lab2_1bit_adder fa2(A[2], B[2], C2, S[2], C3);
lab2_1bit_adder fa3(A[3], B[3], C3, S[3], C4);
endmodule
Related
I have to make a 64 Bit ALU that takes in A and B 64-bit inputs, a carry_in input and outputs a 64bit result along with a 1-bit carry_out. There is also a 5 bit function-select FS. Where FS[0] controls whether B is inverted or not (using a 2to1 mux.) F[1] does the same for the A. And FS[4:2] determines which operation (Adding, subtracting, logical operations, etc) using an 8to1 Mux. Below is the code for the ALU and Testbench.
I'm pretty sure my testbench is good and so is all the separate components for the ALU. I'm not too confident about my top-level where I instantiate and connect all the inputs/outputs. What is causing the high impedance in the waveform?
module ALU(A, B, FS, cin, cout, result);
input [63:0] A, B;
input [4:0] FS;
input cin;
output cout;
output [63:0] result;
eight_one_mux u7 (firstoutA & secoutB, firstoutA | secoutB, sum, firstoutA ^ secoutB,
left, right, 1'b0, 1'b0, FS[4:2], result);
adder u6 (firstoutA, secoutB, cin, sum, cout);
firstmux u1 (A, !A, FS[1], firstoutA);
secmux u2 (B, !B, FS[0], secoutB);
Alu_shifter u5 (A, left, right);
endmodule
//--------------------------------------------------------------------------------//
//These are the two muxes to split into input and inverted input A,B
module firstmux(a, nota, firstS, firstoutA);
input [63:0] a, nota;
input firstS;
output reg [63:0] firstoutA;
always #(a or nota or firstS)
begin
case(firstS)
0 : firstoutA = a;
1 : firstoutA = nota;
default : firstoutA = 1'bx;
endcase
end
endmodule
//<><><><><><><>//
module secmux(b, notb, secS, secoutB);
input [63:0] b, notb;
input secS;
output reg [63:0] secoutB;
always #(b or notb or secS)
begin
case(secS)
0 : secoutB = b;
1 : secoutB = notb;
default : secoutB = 1'bx;
endcase
end
endmodule
//--------------------------------------------------------------------------------//
//This is the Shifter Blocks
module Alu_shifter (shiftA, right, left); //This shifter block shifts the A input once right or left
input [63:0] shiftA;
output [63:0] right;
output [63:0] left;
shift_right w1 ( //instantiate right shifter block
.a_R(shiftA),
.R(right)
);
shift_left w2 ( //instantiate left shifter block
.a_L(shiftA),
.L(left)
);
endmodule
////////><><><><><><><><><><><><><><><///////
module shift_right (a_R, R); // right shifter block
input [63:0] a_R;
output [63:0] R;
assign R = a_R >> 1; //shift A right once (shift in a 0)
endmodule
module shift_left (a_L, L); //left shifter block
input [63:0] a_L;
output [63:0] L;
assign L = a_L << 1; //shift A left once (shift in a 0)
endmodule
//End shifter blocks (3 total modules)
//----------------------------------------------------//////////////////////
//This is the Adder that Adds A, B and cin
module adder(addA, addB, nic, sum, cout);
input [63:0] addA, addB;
input nic;
output [63:0] sum;
output cout;
assign {cout, sum} = addA + addB + nic;
endmodule
//----------------------------------------------------//////////////////////
//This is the 8to1 Mux that decides which operation is put forward
module eight_one_mux(D0, D1, D2, D3, D4, D5, D6, D7, S, out);
input [63:0] D0, D1, D2, D3, D4, D5, D6, D7;
input [2:0] S;
output reg [63:0] out;
always #(D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 or S)
begin
case(S)
0 : out = D0; //And
1 : out = D1; //Or
2 : out = D2; //Adder
3 : out = D3; //xor
4 : out = D4; //lefter
5 : out = D5; //righter
6 : out = D6; //GND
7 : out = D7; //GND
default : out = 1'bx;
endcase
end
endmodule
////////////-------------------------------////////////////////////////////
module ALU_tb();
reg [63:0] A, B;
reg [4:0] FS;
reg cin;
wire cout;
wire [63:0] result;
ALU dut (
.A(A),
.B(B),
.FS(FS),
.cin(cin),
.cout(cout),
.result(result)
);
initial begin
A = 8'b11001100;
B = 8'b11001101;
FS = 5'b01101;
cin = 1;
end
always
#5 cin <= ~cin;
always begin
#5
A <= A + 1;
B <= B + 2;
#5;
end
initial begin
#100 $finish;
end
endmodule
```
Unexpected high impedance (z) values are typically the result of undriven signals, and that is the problem with your code.
adder u6 (firstoutA, secoutB, cin, sum, cout);
In the line above, you connect the 1-bit signal firstoutA to the 64-bit addA input port. This connects firstoutA to addA[0], leaving the other 63 bits undriven. Thus, addA[63:1] are all z.
firstoutA is a 1-bit signal because you did not explicitly declare it. Also, undeclared signals are assumed to be of type wire, which default to z.
It is good practice to declare all signals.
To find all undeclared signals, add this to the top of your code:
`default_nettype none
You should get compile errors like:
Error-[IND] Identifier not declared
Identifier 'firstoutA' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
Error-[IND] Identifier not declared
Identifier 'secoutB' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
First you need to define signals (wire) for connections between modules. For example, you have left and right as outputs of Alu_shifter module and they are connected to firstmux and secmux modules; however, they are not defined in your top module. You should add following signal definitions to your topmodule:
wire [63:0] left,right;
wire [63:0] firstoutA;
wire [63:0] secoutB;
wire [63:0] sum;
Also, eight_one_mux module takes eight 64-bit inputs. However, you set the last two of them as 1'b0. You should change them to 64'b0 as below.
eight_one_mux u7 (firstoutA & secoutB, firstoutA | secoutB, sum, firstoutA ^ secoutB,
left, right, 64'b0, 64'b0, FS[4:2], result);
Finally, !A does not invert all bits of A (same for B). It applies a reduction operation and generates a 1-bit signal (and firstmux module expects a 64-bit signal in its second input port).
How can I check if my 4-bit adder is working properly. If it is then it should display "OK" or if it's not then "NOT". I wrote the code and the bench test which will calculate all possible 4-bit combinations, but i don't know whether the output values are correct and I want to check it. My test bench is already displaying overflow. Here is my code :
module ripple_carry_adder_subtractor(S, C, V, A, B, Op);
output [3:0] S; // The 4-bit sum/difference.
output C; // The 1-bit carry/borrow status.
output V; // The 1-bit overflow status.
input [3:0] A; // The 4-bit augend/minuend.
input [3:0] B; // The 4-bit addend/subtrahend.
input Op; // The operation: 0 => Add, 1=>Subtract.
wire C0; // The carry out bit of fa0, the carry in bit of fa1.
wire C1; // The carry out bit of fa1, the carry in bit of fa2.
wire C2; // The carry out bit of fa2, the carry in bit of fa3.
wire C3; // The carry out bit of fa2, used to generate final carry/borrrow.
wire B0; // The xor'd result of B[0] and Op
wire B1; // The xor'd result of B[1] and Op
wire B2; // The xor'd result of B[2] and Op
wire B3; // The xor'd result of B[3] and Op
xor(B0, B[0], Op);
xor(B1, B[1], Op);
xor(B2, B[2], Op);
xor(B3, B[3], Op);
xor(C, C3, Op); // Carry = C3 for addition, Carry = not(C3) for subtraction.
xor(V, C3, C2); // If the two most significant carry output bits differ, then we have an overflow.
full_adder fa0(S[0], C0, A[0], B0, Op); // Least significant bit.
full_adder fa1(S[1], C1, A[1], B1, C0);
full_adder fa2(S[2], C2, A[2], B2, C1);
full_adder fa3(S[3], C3, A[3], B3, C2); // Most significant bit.
endmodule // ripple_carry_adder_subtractor
module full_adder(S, Cout, A, B, Cin);
output S;
output Cout;
input A;
input B;
input Cin;
wire w1;
wire w2;
wire w3;
wire w4;
xor(w1, A, B);
xor(S, Cin, w1);
and(w2, A, B);
and(w3, A, Cin);
and(w4, B, Cin);
or(Cout, w2, w3, w4);
endmodule // full_adder
module tb_U2_add_sub;
reg [3:0] A;
reg [3:0] B;
wire [3:0] S;
reg Op;
wire V;
integer i, j;
ripple_carry_adder_subtractor U2AS(.A(A), .B(B), .S(S), .Op(Op), .V(V));
always #* if (V == 1) $display($time, " overflow");
initial begin
Op = 0; // Op = 0 ->adder; Op = 1 ->subtractor
for (i=0; i<16; i=i+1) begin
for (j=0; j<16; j=j+1) begin
A = i;
B = j;
#10;
end
end
end
endmodule
You can calculate expected values at testbench and compare them with calculated results from your module. If they are not same, you will now there is an error. In your case,
module tb_U2_add_sub;
reg [3:0] A;
reg [3:0] B;
wire [3:0] S;
reg Op;
wire V;
integer i, j;
ripple_carry_adder_subtractor U2AS(.A(A), .B(B), .S(S), .Op(Op), .V(V));
reg [3:0] S_exp; // expected S value
reg V_exp; // expected V value
initial begin
Op = 0; // Op = 0 ->adder; Op = 1 ->subtractor
for (i=0; i<16; i=i+1) begin
for (j=0; j<16; j=j+1) begin
A = i;
B = j;
// Calculate expected values
S_exp = i+j;
V_exp = (A[3]&B[3]&(~S_exp[3])) | ((~A[3])&(~B[3])&S_exp[3]);
#10;
// Compare expected values with calculated values
if ((S_exp[3:0] !== S) || (V_exp !== V)) begin
// if there is an error, display it and stop simulation
$display("Failed for A=%d,B=%d.\n",A,B);
$stop();
end
end
end
// if there is no error, you will see "Passed"
$display("Passed");
end
endmodule
Here I'm designing a 16-bit CarrySelectAdder
Here is the adder file:
module multiplexer2x1_4 (X, I0, I1, S);
output [3:0] X;
input [3:0] I1;
input [3:0] I0;
input S;
assign X = (S == 1'b0) ? I0 : I1;
endmodule
module multiplexer2x1_1 (X, I0, I1, S);
output X;
input I1;
input I0;
input S;
assign X = (S == 1'b0) ? I0 : I1;
endmodule
module halfAdder(S,Cout,A,B);
output S;
output Cout;
input A;
input B;
xor(S,A,B);
and(Cout,A,B);
endmodule
module fullAdder(S, Cout, A, B, Cin);
output S;
output Cout;
input A;
input B;
input Cin;
wire C1;
wire C2;
wire S1;
halfAdder h1 (S1,C1,A,B);
halfAdder h2 (S,C2,S1,Cin);
or(Cout, C1, C2);
endmodule
module rippleCarryAdder(S, C, A, B, Cin);
output [3:0] S;
output C;
input [3:0] A;
input [3:0] B;
input Cin;
wire C0;
wire C1;
wire C2;
fullAdder f0(S[0], C0, A[0], B[0], Cin);
fullAdder f1(S[1], C1, A[1], B[1], C0);
fullAdder f2(S[2], C2, A[2], B[2], C1);
fullAdder f3(S[3], C, A[3], B[3], C2);
endmodule
module carrySelectAdder(S, C, A, B);
output [15:0] S;
output C;
input [15:0] A;
input [15:0] B;
wire [11:0] S0;
wire [11:0] S1;
wire C0;
wire C1;
wire C2;
wire C3;
wire C4;
wire C5;
wire C6;
wire C7;
wire C8;
rippleCarryAdder R1 (S[3:0], C0, A[3:0], B[3:0], 0);
rippleCarryAdder R2_1 (S0[3:0], C1, A[7:4], B[7:4], 0);
rippleCarryAdder R2_2 (S1[3:0], C2, A[7:4], B[7:4], 1);
multiplexer2x1_4 mux2 (S[7:4], S0[3:0], S1[3:0], C0);
multiplexer2x1_1 mc2 (C3,C1,C2,C0);
rippleCarryAdder R3_1 (S0[7:4], C4, A[11:8], B[11:8], 0);
rippleCarryAdder R3_2 (S1[7:4], C5, A[11:8], B[11:8], 1);
multiplexer2x1_4 mux3 (S[11:8], S0[11:8], S1[11:8], C3);
multiplexer2x1_1 mc3 (C6,C4,C5,C3);
rippleCarryAdder R4_1 (S0[11:8], C7, A[15:12], B[15:12], 0);
rippleCarryAdder R4_2 (S1[11:8], C8, A[15:12], B[15:12], 1);
multiplexer2x1_4 mux4 (S[15:12], S0[11:8], S1[11:8], C6);
multiplexer2x1_1 mc4 (C,C7,C8,C6);
endmodule
and this is the testbench:
module carrySelectAdder_testBench;
reg [15:0] a;
reg [15:0] b;
wire [15:0] sum;
wire carry;
carrySelectAdder sl (sum[15:0],carry,a[15:0],b[15:0]);
initial
begin
$monitor("%b \t %b",sum,carry);
assign a = 16'b1001010110010101;
assign b = 16'b1001010111110101;
$finish;
end
endmodule
it gives me size match error in port 5 in the rippleCarryAdder, What is wrong?
design.sv: L78: warning: Port sizes don't match in port #5 design.sv:
L80: warning: Port sizes don't match in port #5 design.sv: L81:
warning: Port sizes don't match in port #5 design.sv: L86: warning:
Port sizes don't match in port #5 design.sv: L87: warning: Port sizes
don't match in port #5 design.sv: L92: warning: Port sizes don't match
in port #5 design.sv: L93: warning: Port sizes don't match in port #5
The issue is that you tied the input port of your rippleCarryAdder instance to 0 instead of 1'b0.
0 is an unsized literal constant number here, meaning you did not define the bit-width of this constant. When looking at Section 5.7.1 (Integer literal constants) of the the SystemVerilog LRM, we find that:
The number of bits that make up an unsized number (which is a simple decimal number or a number with a base specifier but no size specification) shall be at least 32. Unsized unsigned literal constants where the high-order bit is unknown (X or x) or three-state (Z or z) shall be extended to the size of the expression containing the literal constant.
Hence, the compiler is interpreting your RTL as if you connected a 32-bit (or more) constant to the 1-bit input port of rippleCarryAdder.
This is my design code
module lab2_4bit_adder(
input [3:0] A,
inout [3:0] B,
input C0,
input [3:0] B1,
input Switch,
inout [3:0] B2,
output [3:0] S,
output C4
);
wire C1;
wire C2;
wire C3;
assign B2 = ~B1 + 1'b1;
assign B = (Switch == 0)? B1:B2;
assign B = (Switch == 1)? B2:B1;
assign B = Switch? B2:B1;
lab2_1bit_adder fa0(A[0], B[0], C0, S[0], C1);
lab2_1bit_adder fa1(A[1], B[1], C1, S[1], C2);
lab2_1bit_adder fa2(A[2], B[2], C2, S[2], C3);
lab2_1bit_adder fa3(A[3], B[3], C3, S[3], C4);
endmodule
This is my simulation
module combine_simulation(
);
reg [3:0] A;
reg [3:0] B1;
reg C0;
reg Switch;
wire [3:0] S;
wire C4;
wire [3:0] B;
wire [3:0] B2;
lab2_4bit_adder dut(A,B1,C0,Switch,S,C4,B2,B);
initial begin
A=4'b0101; B1=4'b0011; C0=1'b0; Switch=0; #10;
A=4'b0011; B1=4'b1001; C0=1'b0; Switch=0; #10;
A=4'b0100; B1=4'b1010; C0=1'b1; Switch=0; #10;
A=4'b0101; B1=4'b0011; C0=1'b0; Switch=1; #10;
A=4'b0011; B1=4'b1001; C0=1'b0; Switch=1; #10;
A=4'b0100; B1=4'b1010; C0=1'b1; Switch=1; #10;
end
endmodule
Simulation returns the errors
[USF-XSim 62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'F:/lab2/lab2.sim/sim_1/behav/elaborate.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
[VRFC 10-529] concurrent assignment to a non-net B1 is not permitted ["F:/lab2/lab2.srcs/sim_1/new/combine_simulation.v":37]
[VRFC 10-1146] non-net variable cannot be connected to inout port B ["F:/lab2/lab2.srcs/sim_1/new/combine_simulation.v":37]
[XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
How can i correct the errors?
The error messages are pretty helpful: " non-net variable cannot be connected to inout port B". You cannot connect a variable (ie a reg) to an inout port; connections to an inout port must be a net (the most common net type by far being a wire).
Your code needs some work. A 4-bit adder should not require bidirectional ports (ie inouts). Surely, A, B1 (the operands) and C0 (the carry-in) should be the inputs and S (the sum) and C4 (the carry out) should be the outputs. Why are B and B2 ports at all?
And what are these lines doing?
assign B = (Switch == 0)? B1:B2;
assign B = (Switch == 1)? B2:B1;
You are driving B 3 times.
I am trying to simulate the following circuit using veriwell. However, simulation results is giving me the value of each net as x. Since the circuit does not have any backward loop, I guess every net should have either 1 or 0 signals.
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
wire NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule
module s27(clk, in1, in2, GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2);
input clk, in1, in2;
output GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2;
wire AO, BO, CO, DO, EO, FO;
wire a1, a2, a3, a4;
wire o1, o2;
dff A(clk,AO,in1);
dff B(clk,BO,in2);
dff C(clk,CO,o1);
dff D(clk,DO,a1);
dff E(clk,EO,a2);
dff F(clk,FO,o2);
dff G(clk,GO,a3);
dff H(clk,HO,a4);
and AND2_1 (a1, AO, CO);
and AND2_2 (a2, CO, BO);
and AND2_3 (a3, AO, FO);
and AND2_4 (a4, FO, BO);
or OR2_1(o1, AO, BO);
or OR2_2(o2, DO, EO);
endmodule
I am using the following testbench (generated using a script):
`timescale 1ns/1ps
module testbench;
parameter sOutFileName = "beSimOut.txt";
parameter nVectorWidth = 3;
parameter nVectorSpace = 1000;
parameter nSimCycle = 10;
/* simulation memory */
reg [nVectorWidth - 1:0] mSimMemory [nVectorSpace - 1:0];
/* simulation vector */
reg [nVectorWidth - 1:0] vSimVector;
/* bench variables */
integer nOutFile, nIndex;
/* connection variable declarations */
wire clk, in1, in2, G0, H0, A0, B0, C0, D0, E0, F0, a1, a2, a3, a4, o1, o2;
/* drive inputs */
assign clk = vSimVector[2];
assign in1 = vSimVector[1];
assign in2 = vSimVector[0];
/* simulation memory population routine */
task populateSimulationMemory;
begin
for (nIndex = 0; nIndex < nVectorSpace; nIndex = nIndex + 1)
mSimMemory[nIndex] = { $random };
end
endtask
/* simulation */
initial
begin
/* start monitoring */
$monitor($time, ": clk = %b, in1 = %b, in2 = %b, GO = %b, HO = %b, AO = %b, BO = %b, CO = %b, DO = %b, EO = %b, FO = %b, a1 = %b, a2 = %b, a3 = %b, a4 = %b, o1 = %b, o2 = %b", clk, in1, in2, GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2);
/* populate simulation memory */
populateSimulationMemory;
/* open dump file */
nOutFile = $fopen(sOutFileName);
if (nOutFile == 0)
begin
$display("Can't open %s file for dumping. Exiting ...", sOutFileName);
$finish;
end
/* simulate inputs */
for (nIndex = 0; nIndex < nVectorSpace; nIndex = nIndex + 1)
#nSimCycle vSimVector = mSimMemory[nIndex];
#1 $fclose(nOutFile);
nOutFile = 0;
$finish;
end
/* instantiation */
s27 inst (.clk(clk), .in1(in1), .in2(in2), .GO(GO), .HO(HO), .AO(AO), .BO(BO), .CO(CO), .DO(DO), .EO(EO), .FO(FO), .a1(a1), .a2(a2), .a3(a3), .a4(a4), .o1(o1), .o2(o2));
/* dump */
always #(clk or in1 or in2 or GO or HO or AO or BO or CO or DO or EO or FO or a1 or a2 or a3 or a4 or o1 or o2)
if (nOutFile != 0)
$fdisplay(nOutFile, $time, ": clk = %b, in1 = %b, in2 = %b, GO = %b, HO = %b, AO = %b, BO = %b, CO = %b, DO = %b, EO = %b, FO = %b, a1 = %b, a2 = %b, a3 = %b, a4 = %b, o1 = %b, o2 = %b", clk, in1, in2, GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2);
endmodule
Any ideas on why I am not getting the correct output?
Thanks in advance.
The dff is not modeled correctly. With the current dff, M will float (high-Z) when CK is high.
dff should look like this:
not N1 (NCK,CK);
cmos C1 (M,D,NCK,CK);
cmos C2 (M,NNM,CK,NCK);
not N2 (NM,M);
not N3 (NNM,NM);
cmos C3 (NNQ,NNM,CK,NCK);
cmos C4 (NNQ,Q,NCK,CK);
not N3 (NQ,NNQ);
not N4 (Q,NQ);
or as nand gates:
nand DN1 (NM,D,CK);
nand DN2 (M,NM,CK);
nand DN3 (Q,NQ,NM);
nand ND4 (QN,Q,M);
or as behavioral:
always #(posedge CK)
Q <= D;
When I try to compile your code with the VCS simulator, I get a compilation error:
Identifier 'GO' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
In your testbench module, you declare a wire G0 (the number zero), but then you use GO (capital letter O). You should change the zeroes to letter O's.
I don't think this will completely solve your problem, but this was too complicated to fit in a Comment.