Signal is connected to following multiple drivers in verilog - verilog

Question

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:07:59 12/16/2017
// Design Name:
// Module Name: keyscan
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module keyscan(key, clk, reset, keyout);
input [9:0] key;
input clk, reset;
output reg [127:0] keyout;
reg [3:0] keyp [31:0] ;
reg [3:0] key_bcd;
integer i, count;
///////ERROR help me ㅠ.ㅠ
always # (posedge reset) begin
if(reset==1) begin
for(i=0; i<32; i=i+1)begin
keyp[i] <= 4'hF;
end
key_bcd <= 4'b1111;
count <= 0;
end
end
always # (*) begin
case(key)
10'b0000000001 :
begin
key_bcd = 4'b0000; //0
count = count + 1;
end
10'b0000000010 :
begin
key_bcd = 4'b0001; // 1
count = count + 1;
end
10'b0000000100 :
begin
key_bcd = 4'b0010; // 2
count = count + 1;
end
10'b0000001000 :
begin
key_bcd = 4'b0011; // 3
count = count + 1;
end
10'b0000010000 :
begin
key_bcd = 4'b0100; // 4
count = count + 1;
end
10'b0000100000 :
begin
key_bcd = 4'b0101; // 5
count = count + 1;
end
10'b0001000000 :
begin
key_bcd = 4'b0110; // 6
count = count + 1;
end
10'b0010000000 :
begin
key_bcd = 4'b0111; // 7
count = count + 1;
end
10'b0100000000 :
begin
key_bcd = 4'b1000; // 8
count = count + 1;
end
10'b1000000000 :
begin
key_bcd = 4'b1001; // 9
count = count + 1;
end
default : key_bcd = 4'b1111; // ??
endcase
if(count == 32)
count = 0;
end
always# (count) begin
if(key_bcd != 4'b1111)
keyp[count-1] <= key_bcd;
end
always# (posedge clk)begin
keyout = {keyp[31],124'hfffffffffffffffffffffffffffffff};
end
endmodule
ERROR ㅠ.ㅠ
HDLCompiler:1401 - "C:\Users\com603\Desktop\verilog\aqx\keyscanf.v" Line 44: Signal keyp[31][3] in unit keyscanf is connected to following multiple drivers:

Answer 1

you have 2 always block which drive the same register keyp:
always # (posedge reset) begin
if(reset==1) begin
for(i=0; i<32; i=i+1)begin
keyp[i] <= 4'hF; // <<<<<<<<<<<<<<<<<
end
...
and
always# (count) begin
if(key_bcd != 4'b1111)
keyp[count-1] <= key_bcd; // <<<<<<<<<<<<<<<<<
end
In simulation it will produce unpredictible result since the last driver will win. But there is no way to say which one is the last. Synthesis should complain about it.
You need to find a way to combine both statements in the same always block.
First of all you need to synchronize your code using clock. You even have clk as an input, so use with #(posedge clk) in your block.
I guess something like the following should work:
always # (posedge clk or posedge reset) begin
if(reset==1) begin
for(i=0; i<32; i=i+1)begin
keyp[i] <= 4'hF;
end
key_bcd <= 4'b1111;
end
else if(key_bcd != 4'b1111)
keyp[count-1] <= key_bcd;
end