How to run this code in series using verilog - verilog

Question

The following code is compiled and is working in parallel, Please help me to make these code work sequentially, i.e after stage1 counter should reset itself and starts from 0 for the stage2. The following codes has Module1- stage1 and module2-stage2. This is the process flow in which one stage occur after completion of another. For example when stage 1 is done then counter reset itself and then stage 2 starts with count zero.Here stage 1 module has counter that counts till 18 and stage 2 counter counts 8.
module stage1(
input Clk, //50 Hz clock
input x0,
input reset,
output reg y0,y1,y2,y3,y5,y7,y10,y15,
output reg stage1_done
);
reg [15:0] counter = 0;
parameter F = 50;
always# (posedge Clk or posedge reset)
if(reset) begin
counter <= 0;
{y0,y1,y2,y3,y5,y7,y10,y15} <= 8'b00000000;
stage1_done <= 0;
end else begin
if(x0 == 1) begin
if(counter == 18*F)
stage1_done <= 1;
else begin
counter <= counter + 1;
stage1_done <= 0;
end
if(counter >= 1*F && counter < 10*F)
y0 <= 1;
else
y0 <= 0;
if(counter >= 1*F && counter < 17*F)
y1 <= 1;
else
y1 <= 0;
if(counter >= 1*F && counter < 9*F)
y2 <= 1;
else
y2 <= 0;
if(counter >= 11*F && counter < 16*F)
y3 <= 1;
else
y3 <= 0;
if(counter >= 1*F && counter < 18*F)
y5 <= 1;
else
y5 <= 0;
if(counter >= 1*F && counter < 5*F)
y7 <= 1;
else
y7 <= 0;
if(counter >= 1*F && counter < 5*F)
y10 <= 1;
else
y10 <= 0;
if((counter >= 2*F && counter < 9*F) || (counter >= 13*F && counter < 17*F))
y15 <= 1;
else
y15 <= 0;
end
end
endmodule
//Module for stage 2;
module stage2(
input x0,
input Clk, //50 Hz clock
input reset,
output reg y1,y3,y5,
output reg stage2_done
);
reg [15:0] counter = 0;
parameter F = 50;
always# (posedge Clk or posedge reset)
if(reset) begin
counter <= 0;
{y1,y3,y5} <= 3'b000;
stage2_done <= 0;
end
else begin if(x0 == 1) begin
if(counter == 8*F)
stage2_done <= 1;
else begin
counter <= counter + 1;
stage2_done <= 0;
end
if(counter >= 1*F && counter < 8*F)
y1 <= 1;
else
y1 <= 0;
if(counter >= 1*F && counter < 8*F)
y3 <= 1;
else
y3 <= 0;
if(counter >= 1*F && counter < 8*F)
y5 <= 1;
else
y5 <= 0;
end
end
endmodule

Answer 1

If you want a counter from stage2 module to start counting after counter from stage1 finishes, then you have to "inform" it that the other one finished counting. In your case you can use stage1_done signal and feed it to stage2 module. Use this signal as a condition for counter to start counting initially. Also, shouldn't you reset the counter from stage1 back to 0 when you assert stage1_done?

Answer 2

Think of it as a state machine. with 2 or 3 states, i.e. reset, stage1, stage2. You need to think over the conditions which would move from one stage to another. You provided one condition: stage1 counter overflow has to go from stage1 to stage2. There are definitely few question: what happens to stage1 while stage2 is running, what what happens when stage 2 is finished. What happens during reset?
So, I suggest that you create yest another module to implement the state machine logic:
module control(clk, ...);
enum { reset, stage1, stage2} state, next_state;
always_ff #( posedge clk)
case (state)
reset:
if (!resetSig) next_state <= stage1;
else if (resetSig) next_state <= reset;
stage1:
if (stage1Done) next)state <= stage2;
...
endcase
assign state = next_state;
Now in every stage you just use state as an enable condition.
module stage1(clk, state, stageDone, ...)
always_ff
if (state == reset)
do reset
else if (state == stage1)
do stage1
assign stageDone = counter == max_value;
and so on. Yes, you will need to pass extra ports for the state machine controls, but you will make your code much more manageable and readable and confirm to industry practices.