I have a makefile and while attempting to compile it with make -f Makefile.linux it's giving the error:
make: Nothing to be done for 'all'
I've looked around and haven't found a solution to this. Some others have had a similar problem before but their solutions do not seem to work for me.
Here's my code:
FCOMPL=/usr/bin/g77 -m32
FCOM90=gfortran -m32
FFLAGC=-u -Wall -ff2c -fPIC -O
BINDIR=/ami/bin/linux-x86
OLDBIN=/ami/bin/linux-x86/old
LIBDIR=/ami/lib/linux-x86
X11LIB=/usr/X11R6/lib
BLDDIR=./
LIBS=-L/mrao/lib -lutil -lio -lch -lpgplot -L$(X11LIB) -lX11
SOURCE_FILES=./make_sources
include $(SOURCE_FILES)
.SUFFIXES : .f90
.f.o:
$(FCOMPL) -c $(FFLAGC) $<
.f90.o:
$(FCOM90) -c $(FFLAGC) $<
#all:profile
libprofile.a : $(OBJECTS)
ar ru libprofile.a $(OBJECTS)
profile: profile.f90 libprofile.a
$(FCOM90) $(FFLAGC) -o profile.linux profile.f90 \
-L$(BLDDIR) -lprofile \
-L$(LIBDIR) -lsla -lnag77 -lcfitsio $(LIBS)
ln -s profile.linux profile
chmod g+w *.o *.mod *.a profile.linux
install: profile
mv $(BINDIR)/profile $(OLDBIN)/profile
cp -p profile.linux $(BINDIR)/profile
chmod g+w $(BINDIR)/profile
previous:
mv $(OLDBIN)/profile $(BINDIR)/profile
clean:
rm profile.linux profile *.o *.mod *.a
Solved.
This can be fixed by typing:
make clean -f Makefile.linux
followed by
make -f Makefile.linux
Related
I followed this guide to build a cross compiler for Raspberry Pi ARMv7. It works fine (compiles ok hello world) but the problem is I can't use Raspberry Pi libraries such as wiringpi, sqlite etc.
This is my Makefile.
CC = /opt/cross-pi-gcc/bin/arm-linux-gnueabihf-g++
QUOTE := "
CFLAGS = -g -lwiringPi -pthread -lpthread
PROGRAM = lora
OBJDIR = obj
CPP_SRCS += \
src/main.cpp \
src/radio/sx1276/sx1276.cpp \
src/radio/radio.cpp \
OBJ_FILES += \
$(OBJDIR)/main.o \
$(OBJDIR)/sx1276.o \
$(OBJDIR)/radio.o \
all: make_dir $(OBJ_FILES)
$(CC) $(OBJ_FILES) $(CFLAGS) -o $(PROGRAM)
make_dir:
mkdir -p $(OBJDIR)
$(OBJDIR)/main.o: src/main.cpp
$(CC) $(CFLAGS) -c -o $# $<
$(OBJDIR)/service.o: src/service/service.cpp
$(CC) $(CFLAGS) -c -o $# $<
$(OBJDIR)/sx1276.o: src/radio/sx1276/sx1276.cpp
$(CC) $(CFLAGS) -c -o $# $<
$(OBJDIR)/radio.o: src/radio/radio.cpp
$(CC) $(CFLAGS) -c -o $# $<
clean:
rm $(PROGRAM)
rm -rf $(OBJDIR)
The error I'm getting:
/opt/cross-pi-gcc/lib/gcc/arm-linux-gnueabihf/8.3.0/../../../../arm-linux-gnueabihf/bin/ld: cannot find -lwiringPi
I copied some libraries from my Pi into a folder on my home dir with this command.
rsync -vR --progress -rl --delete-after --safe-links pi#192.168.1.PI:/{lib,usr,opt/vc/lib} $HOME/raspberrypi/rootfs
Which I found it here.
But I'm not sure how to link them. Did I overlook something?
Note: The piece of code I'm trying to compile was compiling fine on Windows's cross-compiler.
I'm trying to setup a tool-chain on my Linux desktop. I'm using Manjaro.
You have to tell the linker where to look for the libraries.
You can add the flag -L$HOME/raspberrypi/rootfs/usr/lib, or wherever libwiringPi.so is located.
You have to point the compiler to the right headers as well. For that you use the -I flag. E.g. -I$HOME/raspberrypi/rootfs/usr/include. This goes in the CFLAGS of the targets that include wiringPi.h.
Also, -lwiringPi -pthread -lpthread don't belong in the CFLAGS, they are linker flags. You only need them in the target that builds PROGRAM. You could add a separate variable LDFLAGS, for example.
I need to run C project written in Linux on Windows. The project contains the following: main.c, makefile, (.c) and (.h) files under folder (libs), and it includes "GL/glut.h" (openGL).
I have tried run it under Visual Studio, but didn't work out. Now, I am working with NetBeans under MinGW compiler. I did all steps mentioned to make NetBeans use MinGW compiler, but still the makefile doesn't compile, and I can't understand the error behind.
Any help is very appreciated. Thank you.
Find below the makefile:
EXECUTABLE = main
CC = g++
CWD=$(shell pwd)
INCLUDES =
CFLAGS= -O3 -funroll-loops -fomit-frame-pointer #-static -Wall
LIBFLAGS = -L./ -lGL -lGLU -lglut #-L/usr/X11R6/lib # -lXxf86vm
SOURCE_FILES = $(shell find -name \*.c)
INTERM_DIR=obj
all: $(EXECUTABLE)
clean:
$(RM) -rf $(INTERM_DIR) $(EXECUTABLE)
.PHONY: clean
$(INTERM_DIR) :
mkdir -p $#
$(INTERM_DIR)/%.dep: %.c
mkdir -p `dirname $#`
echo -n `dirname $#`/ > $#
$(CC) $(CFLAGS_COMMON) $< -MM | sed -r -e 's,^(.*)\.o\s*\:,\1.o $# :,g' >> $#
ifneq ($(MAKECMDGOALS),clean)
-include $(SOURCE_FILES:./%.c=./$(INTERM_DIR)/%.dep)
endif
$(INTERM_DIR)/%.o: ./%.c
mkdir -p `dirname $#`
$(CC) $(CFLAGS) -c $< -o $#
$(EXECUTABLE): $(SOURCE_FILES:./%.c=./$(INTERM_DIR)/%.o)
mkdir -p `dirname $#`
$(CC) $^ $(LIBFLAGS) -o $#
The error I got:
C:\cygwin64\bin\bash.exe -c 'C:/Program Files/mingw-w64/x86_64-7.1.0-posix-seh-rt_v5-rev0/mingw64/bin/gcc.exe' -MM
gcc.exe: fatal error: no input files
compilation terminated.
COMPILE FILE FAILED (exit value 1, total time: 306ms)
I believe when you install Visual Studio it gives the option to run with Linux. Another way you might be able to get around this is to use a VM with a Linux OS.
I just came across this makefile, and it's confusing to me:
PROJECT_ROOT = ../..
LIBDIR = $(PROJECT_ROOT)/src/lib
INCDIR = $(PROJECT_ROOT)/include
SRCS = proj_start.c function1.c
LIBS = $(LIBDIR)/libtest.a
OBJS = $(SRCS:.c=.o)
PROJECT = project1
FLAGS = -I$(INCDIR)
CC = gcc $(FLAGS)
.c.o:
$(CC) -c $<
$(PROJECT): $(OBJS)
$(CC) $(OBJS) $(LIBS) -o $#
it: $(PROJECT)
clean:
rm -f $(OBJS) $(PROJECT)
depend: $(SRCS)
$(CC) -M $(SRCS) > dependList
sed -e '1,/^# DO NOT DELETE/!d' Makefile > make.tmp
cat dependList >> make.tmp
mv make.tmp Makefile
rm dependList
# DO NOT DELETE THIS LINE
These are the parts that confuse me:
LIBDIR = $(PROJECT_ROOT)/src/lib
Why is LIBDIR in the root/src/lib library?
Shouldn't it be the root/lib directory (both directories are present in the file hierarchy)?
.c.o:
$(CC) -c $<
What the heck does this do? The "$<" evaluates to .c.o? I see that it is a 'suffix rule' but what are they really used for?
depend: $(SRCS)
$(CC) -M $(SRCS) > dependList
sed -e '1,/^# DO NOT DELETE/!d' Makefile > make.tmp
cat dependList >> make.tmp
mv make.tmp Makefile
rm dependList
# DO NOT DELETE THIS LINE
Why do we need this part? It seems all the dependencies have already been handled...?
Yeah, putting lib/ under src/ looks like a bad, counterintuitive design.
This:
.c.o:
...
is the old way of writing an implicit rule. These days we'd write it like this:
%.o: %.c
...
It's a slightly Rube Goldberg (i.r. clever but over-complicated) way of doing automatic dependency handling. So if foo.c contains the line #include bar.h, this rule will append the line foo.o: bar.h to the makefile. This is actually important.
I am trying to see auto generated dependency the makefile is below:
OBJS := main.o
run : $(OBJS)
$(CC) $(OBJS) -o run -lstdc++
-include $(OBJS:.o=.d)
%.o : %.cpp
$(CC) -c $(CFLAGS) $*.cpp -o $*.o
%.d : %.cpp
#set -e; rm -f $#; \
$(CC) -M $(CPPFLAGS) $< > $#.$$$$; \
echo "creating dependency file."; \
sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
rm -f $#.$$$$
# remove compilation products
clean :
rm -f run *.o *.d*
But the makefile generate a huge list of dependency in main.d but the actual needed is the first few lines. So where I am getting wrong?
Try this instead:
OBJS := main.o
run : $(OBJS)
$(CC) $(OBJS) -o run -lstdc++
-include $(OBJS:.o=.d)
%.o : %.cpp
$(CC) -c -MMD -MP $(CFLAGS) $*.cpp -o $*.o
# remove compilation products
clean :
rm -f run *.o *.d*
So my task is simple, I have created the makefile (New with makefiles) and I want to keep my .o files in a different folder to have a cleaner directory and allow the usage of .o files by others.
I searched and found many solution pointing to using -o $< $#
However, it is giving me that g++: cannot specify -o with -c or -S with multiple files
This is what I want to do:
$(OBJECT_PATH)/file1.o: $(SOURCE_PATH)/file2.cpp $(SOURCE_PATH)/file1.cpp
$(CC) $(CFLAGS) $(SOURCE_PATH)/file2.cpp $(SOURCE_PATH)/file1.cpp -o $#
file1.cpp has #include "file1.h", so from what I read I should include file1.cpp in the dependencies. However, now I can't export to a different directory.
Is there a solution? Or do I have the concept wrong?
Use make -d or even better remake -x to understand what commands are invoked.
Run also make -p to understand what builtin rules are used.
We cannot help you more, because we have no idea if you redefined CFLAGS.
And C++ compilation should better be done with g++ that is CXX and CXXFLAGS, e.g. with (I am extracting this from my make -p output)
LINK.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH)
COMPILE.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
CXX = g++
%.o: %.cc
$(COMPILE.cc) $(OUTPUT_OPTION) $<
I strongly suggest to have CXXFLAGS= -Wall -g at least during the development phase. Learn also to use gdb and valgrind.
You could have the following in your Makefile
CXXFLAGS= -g -Wall
SOURCES=f1.cc f2.cc
SOURCE_PATH=yoursourcedir/
OBJECT_PATH=yourobjectdir/
SRCFILES=$(patsubst %.cc,$(SOURCE_PATH)/%.cc,$(SOURCES))
OBJFILES=$(patsubst %.cc,$(OBJECT_PATH)/%.o,$(SOURCES))
PROGFILE=$(OBJECT_PATH)
.PHONY: all clean
all: $(PROGFILE)
$(PROGFILE): $(OBJFILES)
$(LINK.cc) $^ $(LOADLIBES) $(LDLIBS) -o $#
$(OBJECT_PATH)/%.o: $(SOURCE_PATH)/%.cc
$(COMPILE.cc) $(OUTPUT_OPTION) $<
clean:
$(RM) $(OBJECT_PATH)/*.o $(PROGFILE)
try
$(OBJECT_PATH)/file1.o: $(SOURCE_PATH)/file2.cpp $(SOURCE_PATH)/file1.cpp
$(CC) $(CFLAGS) $^ -c $#
and check that CFLAGS doesn't include -o -c or -s flags
also read about implicit rules. it might help you to orginzie your makefile