I'm trying to test if a wire(s) is on or not to signify if there is an error/overflow in my alu code. Given this code:
output reg[3:0]x; // line 149
output wire error;
output wire overflow;
always #* begin
if(error || overflow) begin
assign x = 4'b1111; // line 155
assign error = ~error;
assign overflow = ~overflow;
end else begin
assign x = opcode;
end
end
I get following error messages:
uut is my instantiation unit in my testbench called main
The code in the example has several issues.
1) you tried to use 'procedural assignments' which is an advanced verilog topic. In other words assign statement inside of an always block. This is not synthesizable, can only be used on reg types, and is there in verilog for very special cases. Do not use it.
You error messages coming from the fact that error and overflow are declared as wire.
2) you are trying to assign inverted version of a value to itself in a non-clocked logic. It will not behave the way you expect. Depending on usage it can either not toggle or will cause an infinite zero-delay loop, or in your case it could just generate a glitch.
So, potentially, your code should look something like the following:
input wire clk; // << you need clock
output reg[3:0]x; // line 149
output wire error;
output wire overflow;
reg error_reg, overflow_reg;
always #(posedge clk) begin
if(error || overflow) begin
x <= 4'b1111; // line 155
error_reg <= ~error;
overflow_reg <= ~overflow;
end else begin
x <= opcode;
end
assign error = error_reg;
assign overflow = overflow_reg;
end
Your using the assign incorrectly. That can be used outside of a always process, but not inside of one.
Also, the type wire, is required for an assign
wire [3:0] x;
assign x = 4'b1111;
Inside the always process, remove the assign statement and just say
reg [3:0] x; // Note that this is assigned as a reg now
always #* begin
if(blah) begin
x = 4'b1111;
end else begin
x = opcode;
end
end
Related
This question already has answers here:
Why is this code getting inferred latches?
(2 answers)
Closed 5 months ago.
I am design a register file module and I am trying to prevent the "inferred latch warning". The module allows for asynchronous reads but synchronous writes. This is what I have designed so far. I generally know what latches are, but can't think of a solution to prevent latches in this case. What would I define as the else statement so that the regfile doesn't create inferred latches?
module register_file (
input wire clk,
input wire rst,
input wire [4:0] raddr_a,
input wire [4:0] raddr_b,
output reg [15:0] rdata_a,
output reg [15:0] rdata_b,
input wire [4:0] waddr,
input wire [15:0] wdata,
input wire we
);
reg [15:0] regfile [0:31];
/// 32 x 16 bit register file
// asynchronous reads
// don't allow read zero register
assign rdata_a = (raddr_a == 5'd0) ? 16'd0 : regfile[raddr_a];
assign rdata_b = (raddr_b == 5'd0) ? 16'd0 : regfile[raddr_b];
integer i;
always #(clk) begin
// reset registers
if (rst) begin
for (i = 0; i < 32; i = i + 1) begin
regfile[i] <= 0;
end
end else begin
// if write enabled, write to register at waddr
if (we == 1'b1) begin
regfile[waddr] <= wdata;
end
end
end
endmodule
Would I set the value to itself? How would I go on preventing an inferring latch? Thanks!
Change always statement from:
always #(clk) begin
to:
always #(posedge clk) begin
I was able to run the posted code on EDA Playground Yosys; it produces latches.
After the change, latches are no longer produced.
Referring to my previous post:
Error (10482): VHDL error: object "select_vector" is used but not declared
I converted my code from VHDL to verilog, but I'm getting this error now:
(Error (10734): Verilog HDL error at SWSelector.v(13): selector is not
a constant),
Any suggestions how do I deal with it? There are 8 possibilities for selector switch which are coming from a decoder. So whenever the value of selector matches 3'b000, I want rq to be assigned to requests. Here is my code:
module SWSelector(
input [7:0] rq,
input [2:0] selector,
output [7:0] request
);
localparam NUM=3'b000;
generate
genvar i;
for(i=0;i<7;i=i+1)
begin: label
if(selector == NUM)
begin
assign request[i] = rq[i];
end
else
begin
assign request[i]=0;
end
end
endgenerate
endmodule
Since your if-statement is in a generate, you're asking the tool to pre-evaluate what selector is set to in order to figure out selecter == NUM evaluates to, but your tool doesn't know because it's a signal, not a parameter.
You want to use the generate to create an always block that you can check the value of selector in, like so:
module SWSelector(
input [7:0] rq,
input [2:0] selector,
output reg [7:0] request
);
localparam NUM=3'b000;
generate
genvar i;
for(i=0;i<7;i=i+1)
begin: label
always #* begin
if(selector == NUM)
request[i] = rq[i];
else
request[i]=0;
end
end
endgenerate
endmodule
Or, as toolic said, you can use a ternary and an assign.
Edit:
Without generate:
module SWSelector(
input [7:0] rq,
input [2:0] selector,
output reg [7:0] request
);
localparam NUM=3'b000;
integer i;
always #* begin
for(i=0;i<7;i=i+1)
if(selector == NUM)
request[i] = rq[i];
else
request[i]=0;
end
endmodule
Why am I getting error "q is not constant"?
module prv(
input [7:0]x,
input [7:0]y,
output [49:0]z
);
wire [24:0]q;
assign z=1;
genvar k;
for (k=50; k<0; k=k-1)
begin
wire [25:0]a;
assign a=0;
assign q= x;
genvar i;
for(i=0; i<8; i=i+1)
begin
if(q[0]==1)
begin
assign a=a+z;
end
assign {a,q}={a,q}>>1;
end
assign z={a[24:0],q};
end
endmodule
I'm afraid that you are trying to use Verilog the wrong way. q is a wire, not a variable (a reg) so it cannot be assigned with a value that includes itself, because that would cause a combinational loop. You are using the assign statement as if it were a regular variable assignment statement and it's not.
Declare a and q as reg, not wire. i and k don't need to be genvars variables, unless you are trying to generate logic by replicating multiple times a piece of code (description). For for loops that need to behave as regular loops (simulation only) use integer variables.
Besides, behavioral code must be enclosed in a block, let it be combinational, sequential, or initial.
A revised (but I cannot make guarantees about its workings) version of your module would be something like this:
module prv(
input wire [7:0] x,
input wire [7:0] y,
output reg [49:0] z
);
reg [24:0] q;
reg [25:0] a;
integer i,k;
initial begin
z = 1;
for (k=50; k<0; k=k-1) begin
a = 0;
q = x;
for (i=0; i<8; i=i+1) begin
if (q[0] == 1) begin
a = a + z;
end
{a,q} = {a,q}>>1;
end
z = {a[24:0],q};
end
endmodule
I know VHDL, and just learning verilog. I'm trying to do a simple assignment with bit shift, and I get undefined 'X' in the result. I don't understand why. This is in simulation with Xilinx ISim software.
This assignment:
assign dout = $signed(data_out >>> shift_bits);
Results in 'X' wherever a '1' should be. For example, if data_out = '00001100', and shift_bits = 1, dout will = '00000XX0'.
Below is the module definition and the assignment operation:
module SensorINV(
input clk,
input [23:0] din,
input idv,
input [4:0] shift_bits,
output [23:0] dout,
output reg odv
);
reg [47:0] data_out = 0; // initialize the output
assign dout = $signed(data_out >>> shift_bits);
// assign dout = data_out[44:21]; // this didn't work either
reg [1:0] state = 0;
always #(posedge clk) begin
case (state)
0 : begin // waiting for new data
...
end
1 : begin
...
data_out <= data_out + temp1_w;
state <= 2;
end
2 : begin
...
state <= 0;
end
default : state <= 0;
endcase
end
The problem turned out to be conflicting drivers of dout, only one of which was shown in the code above. In the next module up, where this one was instantiated (not shown), I had a line like this:
wire [23:0] dout = 0;
This created a continuous assignment, not an initialization value. This conflict didn't show up in simulation until I tried to make dout non-zero. If it were a register reg, it would be an initialization value, but in this case it was a wire. Got rid of the continuous assign = 0, and problem solved.
Can you tell me why this simple verilog program doesn't print 4 as I want?
primitive confrontatore(output z, input x, input y);
table
0 0 : 1;
0 1 : 0;
1 0 : 0;
1 1 : 1;
endtable
endprimitive
comparatore :
module comparatore (r, x, y);
output wire r;
input wire [21:0]x;
input wire [21:0]y;
wire [21:0]z;
genvar i;
generate
for(i=0; i<22; i=i+1)
begin
confrontatore t(z[i],x[i],y[i]);
end
endgenerate
assign r = & z;
endmodule
commutatore :
module commutatore (uscita_commutatore, alpha);
output wire [2:0]uscita_commutatore;
input wire alpha;
reg [2:0]temp;
initial
begin
case (alpha)
1'b0 : assign temp = 3;
1'b1 : assign temp = 4;
endcase
end
assign uscita_commutatore = temp;
endmodule
prova:
module prova();
reg [21:0]in1;
reg [21:0]in2;
wire [2:0]uscita;
wire uscita_comparatore;
comparatore c(uscita_comparatore, in1, in2);
commutatore C(uscita, uscita_comparatore);
initial
begin
in1 = 14;
$dumpfile("prova.vcd");
$dumpvars;
$monitor("\n in1 %d in2 %d -> uscita %d uscita_comparatore %d \n", in1, in2, uscita, uscita_comparatore);
#25 in2 = 14;
#100 $finish;
end
endmodule
The issue is in commutatore. You are using initial, which means the procedural block is only executed at time 0. At time 0, the input alpha is 1'bx, meaning temp is not assigned to anything. Instead of initial, use always #* which will execute the procedural block every time alpha changes.
Generally you should not assign statements in procedural blocks. It is legal Verilog however it is often the source of design bugs and synthesis support is limited.
always #*
begin
case (alpha)
1'b0 : temp = 3;
1'b1 : temp = 4;
default: temp = 3'bx; // <-- optional : to catch known to unknown transitions
endcase
end
The reason you are not getting 4 as you expect for an output is because your commutatore uses an initial block with assign statements in it when you wanted an always #* block to perform the combinational logic to get temp. initial blocks only fire once at the beginning of a simulation, while you want continuous assignment to act as combinational logic. Also, the assign statements in the block are not needed, they only make the simulation behave improperly for your purposes (typically, you will never need to use assign inside another block (initial,always,etc) as this has another meaning than simply set x to y.
For example, you really want something like this:
always #(*) begin
case (alpha)
1'b0: temp = 3'd3;
1'b1: temp = 3'd4;
endcase
end
Also, Verilog already has a build XNOR primative so your confrontatore is not needed, you can use xnor instead.