In the test-bench code shown below, I'm observing that the clock signal clk does not toggle as expected.
The clock changes from low to high at time 5, but doesn't toggle after that.
module tb();
reg clk;
initial begin
clk = 'b0;
#100 $finish;
end
always#* #5 clk = ~clk;
endmodule
However, if I remove #* from the always#* statement, the clock toggles every 5ns as expected. My question is why doesn't the process block always#* get triggered after the first change?
Note: I've tested the code in NCSIM and VCS, I don't think this a simulator issue.
The accepted answer is wrong - the always is initially triggered by the assignment to 0 in the initial block, so you have a perfectly valid question, which is why the always block isn't triggering itself after it ran the first time (and it clearly did run, because clk is set to 1).
Run the code below - you'll see that it works as expected if you change the blocking assignment to a non-blocking one, or if you use an intra-assignment delay instead of your delay control (clk = #5 ~clk). So, this is a scheduling issue. You might intuitively expect that your process would only trigger once, because the eventual blocking assignment and the process evaluation effectively occur in the same delta, so the blocking assignment could potentially be lost. However, I can't see a specific justification in the LRM. The delay control turns into a future inactive event, and the scheduler eventually executes it, creating an update event, which updates clk (you see this happen once). This should then create an evaluation event for the process, because it's sensitive to clk, but it's not doing this. The scheduling section is (very) woolly, and doesn't really cover this. Mentor would probably give you their version of what's going on if you ask them. VHDL avoids this issue by making all signal assignments non-blocking.
module tb();
reg clk1, clk2, clk3;
initial begin
$monitor($time,, "clk1 = %b; clk2 = %b, clk3 = %b", clk1, clk2, clk3);
clk1 = 1'b0;
clk2 = 1'b0;
clk3 = 1'b0;
#100 $finish;
end
always #*
#5 clk1 = ~clk1;
always #*
#5 clk2 <= ~clk2;
always #(clk3)
clk3 <= #5 ~clk3;
endmodule
clock generators are usually implemented in one of 2 ways:
using always with no sensitivity list, as you already tried:
always #5 clk = ~clk;
the always block without sensitivity list will loop forever and would cause your simulation to hang if it has no #delays inside. Though the latter make it perfect for the clock generator.
use forever loops in your initial block:
initial begin
forever
#5 clk = ~clk;
end
the above code works the same way as the previous always.
The problem is always#(*) will not be sensitive to signals written inside it. So in your case, the implicit sensitivity of the always block doesn't have "clk" in it. Rather it is not sensitive to any signal at all.
Related
i know high level async reset can be achieved like:
always#(posedge clk or posedge rst)
begin
if (rst==1)
but how to realize posedge async reset, which means the moment reset edge coming up, the logic in always block reset immediately?
i wrote the logic below:
always#(posedge clk or posedge rst)
begin
rst_pre<=rst;
if(!rst_pre && rst) // to test if rst is posedge
//execute reset logic here...
but the question is, the always block was triggered in a unexpected high frequency, i finally figured out that although there was only 1 posedge of rst, the always block was triggered by rst signal much more than 1 time.
(tested using altera cyclone 10LP with quartus 18)
I think the method i used to achieve posedge async reset is not stable, can anyone tell me what can i do to solve this?
What you are trying to achieve is a asynchronous reset. It can be posedge or negedge.
always#(posedge clk or posedge rst)
begin
if (rst)
// do the reset
else begin
// your normal execution logic
end
end
If you want to use negedge reset then you can use:
always#(posedge clk or negedge rst)
begin
if (~rst)
// do the reset
else begin
// your normal execution logic
end
end
Other than that, there is nothing complicated on reset. Both on these occasions, on posedge/negedge of rst, block will get triggered and it will do the reset.
The very first code snippet which you call "high level async reset" logic is "posedge asynchronous reset logic".
The code snippet specified a active high asynchronous reset signal rst. "active high" + "asynchronous" means signals generated by this always block are reset immediately when rst asserts.
As soon as you include "posedge/negedge reset" in the sensitivy list, and the reset condition inside the always block has priority over the rest of the sequential logic, it is asynchronous:
always # (posedge clk_i, posedge arst_i) begin
if(arst_i) begin
...this condition has to be first
end
else begin
...normal sequential logic
end
end
Use "posedge" for active-high reset, and "negedge" for active-low reset.
Extra note: Sometimes it is also useful to have a reset synchronizer. This synchronized "soft reset" should be included in the normal sequential logic and it would help to have everything synchronized with the clock. By doing this you would have a first asynchronous reset condition, and the last synchronized reset would avoid any metastabiliy problems regarding the asynchronous condition.
This is a simple SV program (I know an arbiter is much more complex, pardon me for naming this as one), but I don't know how the line repeat(4) #ar.cb; keeps controlling the entire clock. If I comment out that line, the clock stops even though I have put it in an 'always' block inside the top module. I can't understand how this works.
testbench.sv
interface arb_if(input bit clk);
logic [1:0] request;
logic [1:0] grant;
logic reset;
clocking cb #(posedge clk);
output request;
input grant;
endclocking
modport DUT(input request,clk,reset,output grant);
modport TB(clocking cb,output reset); endinterface
program automatic test(arb_if.TB ar);
initial begin
ar.reset <= 1;
ar.cb.request<=$urandom;
$display("[%0t]Request is sent",$time);
repeat(4) #ar.cb;
$display("[%0t]Grant=%0d",$time,ar.cb.grant);
end endprogram
module top;
bit clk;
always #5 clk=~clk;
arb_if arb(clk);
test tb(arb);
arbit a1(arb,clk); endmodule
design.sv
module arbit(arb_if.DUT arbiter,input bit clk); always #(posedge clk)
if(arbiter.reset==0)
arbiter.grant<=2'bxx;
else
#1 arbiter.grant<=arbiter.request;
endmodule
And in the design, the grant does not get assigned till the next cycle even if I use a blocking assignment (unless I give #1, in which case it does, of course after the delay).
I am struggling with understanding the synchronous circuit timings. It'd be a great help if someone can clear this up for me.
Without #1:
With #1:
The program terminates the simulation.
From IEEE Std 1800-2017, section 24.3 The program construct:
When all initial procedures within a program have reached their end,
that program shall immediately terminate all descendent threads of
initial procedures within that program. If there is at least one
initial procedure within at least one program block, the entire
simulation shall terminate by means of an implicit call to the $finish
system task immediately after all the threads and all their descendent
threads originating from all initial procedures within all programs
have ended.
With the repeat statement, the simulation ends at time 35. It waits for 4 positive edges of clk, then implicitly calls $finish.
Without the repeat statement, the simulation ends at time 0. It doesn't wait for any clk edges, then implicitly calls $finish.
I have problem with my Verilog code. I have 2 clocks - one 100kHz, second 10kHz. I'd like to toggle LED with 100kHz frequency only when 10kHz is HIGH. But my output is still low. This is my code:
module LED_toggle(
input clock_100kHz,
input clock_10kHz,
output reg LED_PIN,
);
initial begin
LED_PIN <= 1'b0;
end
always begin
if(clock_10kHz) begin
LED_PIN = 1'b1;
#(posedge clock_100kHz);
LED_PIN = 1'b0;
#(posedge clock_100kHz);
end
else begin
LED_PIN = 1'b0;
end
end
endmodule
I know that I can do this in other way (like trigger on 100kHz edge and check state ot 10kHz), but I try to understand why #(posedge clock_100kHz); don't act like I would expect. I also try wait(clock_100kHz) insted, but this also don't work.
I'm sure that my clocks are configured properly, because this code works like I expect:
module LED_toggle (
input clock_100kHz,
input clock_10kHz,
output reg LED_PIN,
);
initial begin
LED_PIN <= 1'b0;
end
always begin
if(clock_10kHz) begin
LED_PIN = ~LED_PIN;
end
else begin
LED_PIN = 1'b0;
end
end
endmodule
but I try to understand what is wrong with my wait conditions.
It would likely be best if you built this more like HW instead of SW. Your always begin blocks act more like a behavioral model than a HW representation.
It looks like, based on the first snippet that you actually want the LED to run at 50kHz (since you are toggling the LED output on each posedge of the 100kHz)? This would be what I would do, for 100kHz:
assign LED_PIN = clock_10kHz & clock_100Hz;
For 50kHz
always #(posedge clock_100kHz) begin
if(clock_10kHz) LED_PIN <= ~LED_PIN
else LED_PIN <= 1'b0;
end
What the first snippet does is just use the 10kHz clock as a gate and basically the 100kHz clock directly drives the LED.
The second snippet still uses the 10kHz clock as a gate, but there is a register built that is clocked with the 100kHz clock that drives the LED_PIN output. This will make the effective toggling of the LED 50kHz instead of the 100kHz you described/desired, but this matches your behavioral in your first snippet. I'm making an assumption that these clocks are synchronous, but really that gate should be synchronized into the 100kHZ clock domain, but that's a different topic.
always begin is really a behavioral construct. It is essentially something that say "always do this, and do it as fast as I say". In your example, I'm not sure how the simulator didn't just run away when the clock_10kHz was low. Many simulators would see no time statement (such as a #delay or #()) and try to compute that as many times as possible, or just error if it was smart enough to see an infinite loop. Remember that verilog is an event based language. In your code, there are cases where you don't have any "Events", just actions that should happen. This can, and will cause you some grief. If you've done other programming languages, and start verilog, this is usually the hardest part to grasp, but when you do, it makes much more sense.
Hopefully this helps!
I am trying to make a module that performs the twos complement of a value if the msb is 1. It works in cadence, however when I try to synthesize it I get the following error:
Cannot test variable X_parallel because it was not in the event expression or with wrong polarity.
The code for the module is as follows:
module xTwosComp (X_parallel, Clk, Reset, X_pos);
input [13:0] X_parallel;
input Clk, Reset;
//wire X_msb; //was an attempt at fixing the problem
output [13:0] X_pos;
reg [13:0] X_pos;
//assign X_msb=X_parallel[13];//failled attempt at fixing
always # (posedge Clk or posedge Reset)
begin
if (X_parallel[13]) begin
X_pos = ~(X_parallel) +1;
end else begin
X_pos = X_parallel;
end
end
endmodule
You are missing your reset statement. Not sure if this fixes the exact error, but synthesizers expect code to determine what events are asynchronous when there is more than one edge event.
You need an if (Reset) begin X_pos <= 14'b0; else before the if (X_parallel[13]). Otherwise posedge Reset is treated as another clock and not a asynchronous reset. This will confuse the synthesizer.
FYI: flops should be assigned with non-blocking assignments (<=). It will save you from debugging false race condition and RTL to gates simulation mismatches.
After countless hours I have figured it out. It was because i was not referencing Clk or Reset in my always block.
Thanks to anyone who considered the issue.
Thanks Greg for your answer, although I figured out how to make it work I am very glad for your response since it cleared up why it works now. Thanks!
always clk <= #5 !clk;
Seems this doesn`t work and get a "out-of-memory" errors with VCS
What's the reason behind this? I have the feeling the VCS can't get out of the event it scheduled for clk. but don't know why?
You are getting an "out-of-memory" error because it is an non-blocking infinite loop adding future events to the scheduler.
always is functionally equivalent to initial while(1) (an infinite loop). <= #5 doesn't consume time, it schedules an update in the future. There is no time blocking delays in the loop.
Without a time blocking delay the simulator keeps executing the same loop in the same time step. The simulate will not move to the next time step until all operations in the current time step are complete or suspended. Eventually the simulator will run out of memory and error out. Some simulators may exit out early if an infinite loop is detected.
Typically, clocks are generated with LHS delays and with blocking statements. Examples:
reg clk = 1'b1; // or 1'b0
always #5 clk = !clk;
or
reg clk;
initial begin
clk = 1'b1; // or 1'b0
forever #5 clk = !clk;
end
I get "out-of-memory" errors with both VCS and Incisive.
It is more conventional to have the delay on the LHS:
reg clk = 0;
always #5 clk <= !clk;