I wanna create divisible by 6 module in verilog using divisible by 2 module and divisible by 3 module, I grasped the idea, but maybe my verilog grammar is wrong.
the module structure i want to implement is below,
module Divisible_6(input [3:0] a, output out);
using
module Divisible_2(
input [3:0] a,
output out
);
module Divisible_3(
input [3:0] a,
output out
);
and if input is 6(0110), then both divisible_2 and divisible_3 output 1,
and both 1 goes in to the AND gate, then came out with 1.
1 = true, 0 = false.
how can I implement the idea in verilog language?
and help is appreciated, thanks.
input: 1~15
Since I understand question a little bit different than #Morgan, I'd rather try this code:
module Divisible_6(
input [3:0] a,
output out
);
wire out_1, out_2;
assign out = out_1 & out_2;
Divisible_2(
.a (a),
.out(out_1)
);
Divisible_3(
.a (a),
.out(out_2)
);
endmodule
I assume that both Divisible_2 and Divisible_3 take 4-bit input and return boolean value (divisible (1) or not (0)).
You need divisible by 6 design, which can only be obtained, if your input is both divisible by 2 and divisible by 3.
Hence you can use both modules, like the following code.
// Defining the nets
logic out1, out2;
// Continuous Assignment
assign out = out1 & out2;
// Instantiation of 2 modules with instance name d1 & d2
divisible_2 d1 (a, out1);
divisible_3 d2 (a, out2);
Related
i am learning verilog and i am doing practice questions on https://hdlbits.01xz.net/wiki.
one of the questions is:
so my answer was:
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire and_ab;
wire and_cd;
wire or_out;
and(and_ab,a,b);
and(and_cd, c, d);
or(or_out, and_ab, and_cd);
assign out= or_out;
not(out_n,or_out);
endmodule
which is correct without any doubt, but their answer is:
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n );
wire w1, w2; // Declare two wires (named w1 and w2)
assign w1 = a&b; // First AND gate
assign w2 = c&d; // Second AND gate
assign out = w1|w2; // OR gate: Feeds both 'out' and the NOT gate
assign out_n = ~out; // NOT gate
endmodule
my question is how can it be possible they use 'output' wire as an 'input' to an assign in the same module? its not reg to hold it value, not that i know if you can do it with reg as an 'output' type.
Verilog and SV allow the reading of outputs from within a module.
It is different than VHDL which does not allow the same.
I have input like that
a1 = 4'b 1001;
a2 = 4'b 1000;
a3 = 4'b 1111;
say I have a module fulladder that takes three inputs .
I need to call this module with all LSB of input that is like that
fulladder fa (a1[3] , a2[3] , a2[4] )
module full adder (a,b,c, carry , sum);
body -----
endmodule
it works fine with me !!
but but if the fulladder takes input value as array
like bellow then how I can call the module;
module fulladder2 (a , sum, carry)
input [2:0] a;
output sum;
output carry;
body-----
endmoduole
example
fulladder2 f2 (3'b.a(a1[3]a2[3]a2[4]) ?? it shows error can not declare ASCII in binary
or fulladder2 f2 (.a(a1[3],a2[3],a2[4]) ?? it also show error .
I can not convert the module fulladder2 like fulladder .
Use the concatenation operator {...}.
fulladder2 f2( {a1[3],a2[3],a3[3]}, ...
better:
fulladder2 f2 (
.a ( {a1[3],a2[3],a3[3]} ),
.sum (sum),
.carry (carry)
);
Also I noticed two different definitions where you have swapped the carry and sum.
module full adder (a,b,c, carry , sum);
and:
module fulladder2 (a , sum, carry)
That is not a problem if you use the .name(...) port assignment but it is a potential danger if you don't.
As to your nomenclature: what you use is called a 'vector' not an 'array'. In Verilog a one dimensional entity is called a vector. An array is normally two dimensional. A single bit is a wire or reg.
I am trying to write down ALU for verilog.
And there are several error I experiences.
First of all, here is my code:
module yAlu(z, ex, a, b, op);
input [31:0] a, b;
input [2:0] op;
output [31:0] z, ztemp;
output ex;
wire[31:0]a0,a1,a2,a3,a4, atemp;
assign slt = 0;
assign ex = 0;
assign a0 = a & b;
assign a1 = a | b;
assign a2 = a + b;
assign a3 = a - b;
assign a4 = a[31] ^ b[31];
yMux #(32) lo(zLo, a0, a1, op[0]);
yMux #(32) hi(zHi, a2, a3, op[0]);
yMux #(32) temp(atemp, zLo, zHi, op[1]);
assign z = (op[2] == 1) ? a4 : atemp;
assign slt = z;
endmodule
And yAlu.v uses following:
module yMux(z, a, b, c);
parameter SIZE = 2;
output [SIZE-1:0] z;
input [SIZE-1:0] a, b;
input c;
yMux1 mine[SIZE-1:0](z, a, b, c); // 2-bit 2 -to-1 mux and it would be cumbersome to write 32 mux instantiation lines.
endmodule
Lastly above yMux uses following:
module yMux1(z, a, b, c);
output z;
input a, b, c;
wire notC, upper, lower;
// Gates and interconnections for MUX
// if c is 0, z=a.
// if c is 1, z=b
not my_not(notC, c);
and upperAnd(upper, a, notC);
and lowerAnd(lower, c, b);
or my_or(z, upper, lower);
endmodule
Here is is what it tests above yAlu:
module lab8;
reg [31:0] a, b;
reg [31:0] expect;
reg [2:0] op;
wire ex;
wire [31:0] z;
reg ok, flag;
yAlu mine(z, ex, a, b, op);
initial begin
repeat (10) begin
a = $random; b = $random;
if(op==0)
expect = a & b;
else if (op==1)
expect = a | b;
else if (op==2)
expect = a + b;
else if (op==3)
expect = a - b;
else if (op==4)
expect = (a < b) ? 1 : 0;
#1;
if(expect == z)
$display("PASS : expected=%d, a=%d, b=%d, z=%d, op=%d", expect,a,b,z,op);
#1;
$finish;
end
end
endmodule
My questions in order as follow:
Question 1.
Code above only works for 0 and 1. It doesn't work more than that.
For example, on the 2nd source code, there is
a = $random; b = $random;
it doesn't work for this. it only works when a=1 or 0 and b=1 or 0.
Question 2.
I am not sure "slt" function is working correctly. The instructor who teaches this never told me what slt does in lecture but have us design slt, by googling or something.
Question 3.
Whenever I compile, i get following Error. Why is this?
yAlu.v:38: warning: Port 1 (z) of yMux expects 32 bits, got 1.
yAlu.v:38: : Padding 31 high bits of the port.
yAlu.v:39: warning: Port 1 (z) of yMux expects 32 bits, got 1.
yAlu.v:39: : Padding 31 high bits of the port.
yAlu.v:40: warning: Port 2 (a) of yMux expects 32 bits, got 1.
yAlu.v:40: : Padding 31 high bits of the port.
yAlu.v:40: warning: Port 3 (b) of yMux expects 32 bits, got 1.
yAlu.v:40: : Padding 31 high bits of the port.
I can't fix this at all.
I don't even know I am doing it correctly. The manual that directs me to do what it says has no enough explanation as well as no sample output.
I couldn't finish in time anyway, so I guess it doesn't matter but I think I have to know solution for my problems.
Thank you very much if you can help me out.
As shown by the warnings, your port connection width are mismatched. Refer to single warning and other are the same to tackle.
yAlu.v:38: warning: Port 1 (z) of yMux expects 32 bits, got 1.
yAlu.v:38: : Padding 31 high bits of the port.
The module declares ports a,b,c and z, each of width defined by SIZE parameter.
module yMux(z, a, b, c);
parameter SIZE = 2;
output [SIZE-1:0] z;
input [SIZE-1:0] a, b;
Moreover, the SIZE is overridden while instantiating. Now, the value of SIZE is 32. Hence the width of each of a,b,c and z is 32-bits.
yMux #(32) lo(zLo, a0, a1, op[0]);
yMux #(32) hi(zHi, a2, a3, op[0]);
yMux #(32) temp(atemp, zLo, zHi, op[1]);
Here, the ports zLo,zHi is not declared and used directly in port connection.
Referring to IEEE 1800-2012, section 6.10- Implicit declarations:
If an identifier is used in a port expression declaration, then an
implicit net of default net type shall be assumed, with the vector
width of the port expression declaration.
This, if an undeclared identifier is used as a connection to an instance then an implicit net is inferred.
Thus, zLo,zHi are implicitly declared as single bit nets and the rest 32-bits are padded with zeros. Just declare them as follows and all warnings shall be removed:
wire [31:0] zLo,zHi;
To get an error in such a situation, use default_nettype none compiler directive.
For more information, refer Sutherland SV Gotchas paper, section 2.2 and SystemVerilog IEEE 1800-2012 for implicit declarations.
I would like to write a module with a variable number of inputs, i.e. depending on some parameter, the result would be:
module my_module #(LENGTH)(
input clk,
input rst_n,
input [LENGTH-1:0] data_1
);
//...
endmodule
or
module my_module #(LENGTH)(
input clk,
input rst_n,
input [LENGTH-1:0] data_1,
input [LENGTH-1:0] data_2,
input [LENGTH-1:0] data_3
);
//...
endmodule
Would it be possible to do this in Verilog or Systemverilog or would I have to write a script, let's say in Python, in order to generate the code for a specific module with fixed number of inputs? (it might be more than 1000 inputs)
There are no variable number of ports in SystemVerilog, but you could use a port that is a parameterized array.
module my_module #(int LENGTH, DEPTH)(
input clk,
input rst_n,
input [LENGTH-1:0] data[DEPTH]
);
//...
endmodule
Otherwise, you would need to use a script to generate the code.
Use a two dimensional input with a parameterized size. Added a generate for loop that can be used to set signals individually. Although many operations can be done with smart array operations.
module my_module #(SIZE, LENGTH)(
input clk,
input rst_n,
input [SIZE-1:0][LENGTH-1:0] data_in_array,
output [SIZE-1:0][LENGTH-1:0] data_out_array
);
genvar N;
generate for (N=0; N<SIZE; N++) begin :la_coolOps
//Do cool operations here. For example instantiate a module for every data_in
end
//...
endmodule
Edit:
As Mehran Torki points out: The syntax above will work for SystemVerilog only. Verilog does not allow for multiple packed arrays. Use input [LENGTH*SIZE-1:0] data_in_array.
I would add to these other answers that ports are just groupings of wires. While having 3, 1-bit wires named a, b, and c might be easier to read and understand, there is no physical/logical difference between a single, 3-bit wire abc, where abc[0] corresponds to a, abc[1] corresponds to b, and abc[2] corresponds to c.
So, you can always just expand or shrink a single (or multiple) signal(s) to get however many bits you need. It may not be as neat, but it will work. In the receiving module, you can then part-select the bus in whatever manner you like. So, you could have one really long wire the shrinks or expands (wire [(SOME_PARAM*8)-1:0] my_input_wire), or with SystemVerilog an array (wire [7:0] my_input_wire[0:SOME_PARAM-1])
If this is just testbench/verification code, the other thing you could do in SystemVerilog is use a dynamic array
As others said, there is no direct way to do this, but another workaround is to use SystemVerilog interfaces, where you define all the inputs that you want in the interface definition and inside the module only use the ones that correspond to the parameter. Below is a sample:
module my_module #(LENGTH)(
input clk;
input rst_n;
output o;
interface i_data;
);
logic outValue;
generate
case (LENGTH) //Based on the value of LENGTH, use corresponding data
1: outValue = i_data.data_1;
2: outValue = i_data.data_1 + i_data.data_2;
3: outValue = i_data.data_1 + i_data.data_2 + i_data.data_3;
endcase
endgenerate
always #(posedge clk) begin
if (~rst_n)
o <= '0;
else
begin
o <= outValue;
end
endmodule
You can still use a parameterized array for data and a for-generate loop if your outputs are similar.
With System verilog we can import a package instead of having parameterization and define types in the package to be used in the portlist.
module mymodule
import mymodule_pkg::*;
(
input portlist_t portlist
);
endmodule
And define multiple copies of the package with different variants of the port list and compile whichever version is required. eg
package mymodule_pkg;
localparam LENGTH=5;
typedef struct packed {
logic [LENGTH-1:0] data_1,
logic [LENGTH-1:0] data_2,
logic [LENGTH-1:0] data_3
} portlist_t;
endpackage
As with the interface solution there will be situations where you run into issues, like having different iterations of the module instantiated together.
Is it possible to write a module with 3 wires a,b,c that would output either :
z (disconnected) if a=b=c=z
a if a=(0 or 1) and b=c=z
b if b=(0 or 1) and a=c=z
c if c=(0 or 1) and a=b=z
x (dont care) otherwise
In verilog?
If you have three nets all driving the same wire then this will get what you want in simulation:
module three_drive(
input a,
input b,
input c,
output d);
assign d=a;
assign d=b;
assign d=c;
endmodule
However, I don't know what the synthesis would do with that.
It sounds to me like what you really want is to take these three signals and short them together on the input to your FPGA.
If you don't care what the result is if no one is driving it, then nguthrie has the correct answer. If it needs to be x if it's not driven, then you can do:
module three_drive(
input a,
input b,
input c,
output d);
wire temp;
assign temp=a;
assign temp=b;
assign temp=c;
assign d = (temp === 1'bz) ? 1'bx : temp;
endmodule
The above is not synthesizable, but it would get the simulation behavior you are looking for.