*** No rule to make target, Makefile error in Win10 - windows-10

First of all, please, don't just tell me this is a duplicate. I know, but the many questions I've looked through have all been given far too specific answers to assist me, and quite frankly half of it went over my head. I'm very new to using Makefiles and I'm baffled by why mine isn't working.
I'm sure it's something painfully simple but please lend a hand, if you need any more information I'll be happy to try to find it, and bear with me because I'm doing all this from my phone because my university's IT department is run by apes. Currently, this is my Makefile:
Makefile for Assignment 1
finish : main.o
g++ -o finish main.o
main.o :
g++ -c -g -Wall main.cpp
clean :
del main.o
(Sorry, it's not being cooperative, I want to make clear that there is the necessary tab in front of the commands)
I'm running this on Windows 10, using a GNU compiler. From what I can see it looks exactly the same as the example Makefile we were provided, aside from filenames. I know I'm in the right directory, nothing is misspelled, the source file should exist cause I'm staring at it sitting next to the makefile. Those are the generic fixes I remember seeing.
The main.o command works perfectly and compiles the source file, but the other two just give me the error
make: *** No rule to make target 'finish/clean'. Stop.
I'm confused, annoyed, new to Makefiles and Stack Overflow and just looking for a helping hand. Any advice would be greatly appreciated.

I am pasting my example:
CC = g++
CFLAGS = -g
test.o: test.cpp
$(CC) $(CFLAGS) -c test.cpp
last.o: last.cpp
$(CC) $(CFLAGS) -c last.cpp
program: test.o last.o
$(CC) $(CFLAGS) -o program test.o last.o
clean:
$(RM) test.o last.o
I was facing similar issue, Try using $(RM) instead of "del"

Related

How do I correctly link a shared object (.so file) in a makefile when cross-compiling?

I have some C++ code on an openSuse platform that I need to compile to be executed on a different linux-based target. Part of the code is a dynamic library libfoo.so. I compile everything with make and then copy the compiled executable prog together with the libfoo.so to the target. When I then run the executable, I get some errors indicating the libfoo could not be initialized. I've tried everything I could find to tell the executable where it can find the libfoo.so but I still get the error.
Could anybody tell me what I am doing wrong here? I feel like it could be an error in the Makefile.
I am very new to C++ and using Makefiles in general, and on top of it all, the target runs kind of a proprietary linux version, so I cannot provide much information about it. I do have the appropriate compiler for it though.
My directory structure on the openSuse platform:
|src
|--Foolib
|----foolib.h
|----libfoo.so
|--Otherlib
|----otherlib.h
|----otherlib.hpp
|---+OtherlibSrcDirectory
|--bar.cpp
|--bar.h
|--Makefile
Directory structure on the target:
|program
|--libfoo.so
|--prog
My Makefile:
LIBS = -LFoolib -lfoo
INC = -I OtherLib -I Foolib
CXXFLAGS += -lpthread -std=c++11 -D_GLIBCXX_USE_NANOSLEEP $(INC)
LDFLAGS = '-Wl,-rpath,$$ORIGIN'
SRC_FILES = bar.cpp
OBJ = $(SRC_FILES:%.cpp=%.o)
prog: $(OBJ)
$(CXX) $(CXXFLAGS) $(LDFLAGS) $(LIBS) -o $# $^
%.o: %.cpp
$(CXX) $(CXXFLAGS) $(LIBS) -c $<
Basically, bar.h includes Foolib/foolib.h as well as Otherlib/OtherlibSrcDirectory and bar.cpp includes bar.h. Then some functions from foolib.h are called in bar.cpp and they return error values. If necessary I can provide some more insights into the code but I'll leave it out for now to keep it a bit shorter.
Any help would be highly appreciated!
Found my mistake.
libfoo.so was already on the target machine and it was located in the correct folder (/lib). My program had been able to find it without problems.
My mistake: I executed my program on the target machine without root permissions.
Without root permissions, I am not allowed to initialize Foolib.
sudo ./prog fixed everything.

Primitive makefile failure for compiling

I am trying to learn makefile, but I fail badly.
One example (which is very primitive) but I should understand it to go ahead is this one
f90_simple: f1.o
gfortran f1.o
mv a.out f90_simple
f90_simple.o: f1.f90
gfortran -c f1.f90
it does not work, and I get this error
I get this error
make: *** No rule to make target `f1.o', needed by `f90_simple'. Stop.
could you please advise me?
thanks
Your first rule says that before f90_simple can be built, the target f1.o must be built.
But there's no rule in your makefile that tells make how to build the target f1.o, and make can't find any built-in rule that can build it (based on the source files make has available), so it prints that error.
You do have a rule that tells make how to build a target f90_simple.o... but that's not the target make is looking for. Most likely you want your makefile to either be:
f90_simple: f1.o
gfortran $^
mv a.out $#
f1.o: f1.f90
gfortran -o $# -c $<
or else:
f90_simple: f90_simple.o
gfortran $^
mv a.out $#
f90_simple.o: f1.f90
gfortran -o $# -c $<
but you can't mix and match them, or make doesn't know what to do.
I think you would really benefit from reading at least the introductory chapters in The GNU Make Manual.

Struggling with a GCC Makefile

I am trying to write what I thought would be quite a simple Makefile and I'm just baffled! I'm not a makefile writer, but I thought I understood them enough to be able to get a simple one working.
Okay, I have a small project in a directory and also in this directory is a libs directory containing many .c files. What I'm trying to do is write a makefile that will build the contents of the /libs directory into a static lib file in the /libs directory and then compile a few source files in the / directory and link it against the built .a file.
I'm sure someone's going to suggest "why not use cmake", but that's not answer I'm looking for (waves hand like a Jedi.. ehehehehe)
CC = gcc
CFLAGS = -Wall
SOURCES = lzx.c csum.c dirs.c listner.c tree.c
OBJECTS = $(SOURCES:.c=.o)
TARGETLIB = libs/mylib.a
TARGET = TestApp
libs/%.o : libs/%.c
$(CC) $CFLAGS -c $<
$(TARGETLIB) : $(OBJECTS)
ar rcs $# $^
$(TARGET) :
$(CC) $CFLAGS Source1.cpp Source2.cpp -llibs/mylib.a -o $#
My understanding was that the first recipe, would compile all the .c files into objects, but it seems to compile the first .c file and then stop.
Any help anyone could give me would be appreciated.
Since Your final app is TARGET, You should make it first Makefile rule. And since it also depends on TARGETLIB it should be given as dependency, like so:
$(TARGET): $(TARGETLIB)
$(CC) $(CFLAGS) Source1.cpp Source2.cpp -Lmylib -o $#
next I assume that *.c files You mentioned are lib files. Thus You will need a prefix to them, since You want to specify them by hand, not via wildcard or rule.
OBJECTS = $(addprefix(libs, $(SOURCES)):.c=.o)
and last thing that comes to my mind is library name, which supposed to be libSOMENAME.a (well, linker searches for this name in path and -Lotherpaths). So we have:
TARGETLIB = libs/libmylib.a
summing it all up:
CC = gcc
CFLAGS = -Wall
SOURCES = lzx.c csum.c dirs.c listner.c tree.c
OBJECTS = $(addprefix(libs, $(SOURCES)):.c=.o)
TARGETLIB = libs/libmylib.a
TARGET = TestApp
$(TARGET) : $(TARGETLIB)
$(CC) $(CFLAGS) Source1.cpp Source2.cpp -static -L./libs -lmylib -o $#
$(TARGETLIB) : $(OBJECTS)
ar rcs $# $^
And yes, this could be written much better, but I assume if You wanted to learn more about Makefiles or linker, and not just shown where You made mistakes, You'd know how to find manual pages.

Cannot compile with makefile - undefined reference to `boost::re_detail

I got an assignment to improve running time of some code. The only problem is, I can't even compile it to run it on my machine in the first place. Every time I try, it stops somewhere in the midst of compiling saying this:
"undefined reference to `boost::re_detail::put_mem_block(void*)'
collect2: ld returned 1 exit status make: * [cpu] Error 1"
This is how makefile looks:
SHELL = /bin/bash
OBJECTS = main.o atom.o molecule.o charges.o pdb.o asa.o amino.o chain.o addition.o string_operation.o pdb_peptide.o protein_chain.o residue_atom.o chain_residue.o residue_contact.o atom_grid.o circles.o atom_space_calculations.o
OBJDIR = obj
VPATH = src:src/ext:$(OBJDIR)
CFLAGS = -O3 -Wall -lm -lboost_regex -L/usr/local/boost/lib
HDIRS = src,src/ext,src/qt_redistributable, usr/lib, usr/local/lib, usr/local/lib/include/boost, /usr/local/lib/lib/
IOPTS = $(addprefix -I, $(HDIRS))
cpu : $(addprefix $(OBJDIR)/, $(OBJECTS) $(CPUOBJS))
g++ $(CFLAGS) -o mcpu $^
$(OBJDIR)/%.o : %.cpp
g++ $(CFLAGS) $(IOPTS) -c $< -o $#
clean :
rm obj/*.o $(PROG)
I'm using Linux Mint x64 and I have tried everything I googled out. Installed the whole boost library in usr/local/lib (for no obvious reason because it didn't help), tried to edit LD PATH (I'm very new to Linux and I have no idea if that went right) and lots of stuff, but this thing doesn't seem to go through. Any help appreciated.
One problem with your makefile happens when you link your program. As you can see in these questions with g++ the order of your arguments at link time is really important. You need to put your libraries after your object files. One easy way to solve would be separating your linker flags (LDFLAGS) from the compiler flags (CFLAGS), and then putting LDFLAGS after $^ (your object files) in the link command.
CFLAGS = -O3 -Wall
LDFLAGS = -L/usr/local/boost/lib -lm -lboost_regex
cpu : $(addprefix $(OBJDIR)/, $(OBJECTS) $(CPUOBJS))
g++ $(CFLAGS) -o mcpu $^ $(LDFLAGS)
$(OBJDIR)/%.o : %.cpp
g++ $(CFLAGS) $(IOPTS) -c $< -o $#
As can be seen in the Catalogue of Built-In Rules:
Linking a single object file
n is made automatically from n.o by running the linker (usually called
ld) via the C compiler. The precise recipe used is:
$(CC) $(LDFLAGS) n.o $(LOADLIBES) $(LDLIBS)
and Variables Used by Implicit Rules:
LDFLAGS
Extra flags to give to compilers when they are supposed to invoke the linker,
ld, such as -L. Libraries (-lfoo) should be added to the LDLIBS variable
instead.
So in this case -lboost_regex should be set or added to LDLIBS, not LDFLAGS.

Linux: modpost does not build anything

I am having problems getting any kernel modules to build on my machine. Whenever I build a module, modpost always says there are zero modules:
MODPOST 0 modules
To troubleshoot the problem, I wrote a test module (hello.c):
#include <linux/module.h> /* Needed by all modules */
#include <linux/kernel.h> /* Needed for KERN_INFO */
#include <linux/init.h> /* Needed for the macros */
static int __init hello_start(void)
{
printk(KERN_INFO "Loading hello module...\n");
printk(KERN_INFO "Hello world\n");
return 0;
}
static void __exit hello_end(void)
{
printk(KERN_INFO "Goodbye Mr.\n");
}
module_init(hello_start);
module_exit(hello_end);
Here is the Makefile for the module:
obj-m = hello.o
KVERSION = $(shell uname -r)
all:
make -C /lib/modules/$(KVERSION)/build M=$(shell pwd) modules
clean:
make -C /lib/modules/$(KVERSION)/build M=$(shell pwd) clean
When I build it on my machine, I get the following output:
make -C /lib/modules/2.6.32-27-generic/build M=/home/waffleman/tmp/mod-test modules
make[1]: Entering directory `/usr/src/linux-headers-2.6.32-27-generic'
CC [M] /home/waffleman/tmp/mod-test/hello.o
Building modules, stage 2.
MODPOST 0 modules
make[1]: Leaving directory `/usr/src/linux-headers-2.6.32-27-generic'
When I make the module on another machine, it is successful:
make -C /lib/modules/2.6.24-27-generic/build M=/home/somedude/tmp/mod-test modules
make[1]: Entering directory `/usr/src/linux-headers-2.6.24-27-generic'
CC [M] /home/somedude/tmp/mod-test/hello.o
Building modules, stage 2.
MODPOST 1 modules
CC /home/somedude/tmp/mod-test/hello.mod.o
LD [M] /home/somedude/tmp/mod-test/hello.ko
make[1]: Leaving directory `/usr/src/linux-headers-2.6.24-27-generic'
I looked for any relevant documentation about modpost, but found little. Anyone know how modpost decides what to build? Is there an environment that I am possibly missing?
BTW here is what I am running:
uname -a
Linux waffleman-desktop 2.6.32-27-generic #49-Ubuntu SMP Wed Dec 1 23:52:12 UTC 2010 i686 GNU/Linux
Edit
Here is make ran with V=1:
make -C /lib/modules/2.6.32-27-generic/build M=/home/waffleman/tmp/mod-test modules
make[1]: Entering directory `/usr/src/linux-headers-2.6.32-27-generic'
test -e include/linux/autoconf.h -a -e include/config/auto.conf || ( \
echo; \
echo " ERROR: Kernel configuration is invalid."; \
echo " include/linux/autoconf.h or include/config/auto.conf are missing."; \
echo " Run 'make oldconfig && make prepare' on kernel src to fix it."; \
echo; \
/bin/false)
mkdir -p /home/waffleman/tmp/mod-test/.tmp_versions ; rm -f /home/waffleman/tmp/mod-test/.tmp_versions/*
make -f scripts/Makefile.build obj=/home/waffleman/tmp/mod-test
gcc -Wp,-MD,/home/waffleman/tmp/mod-test/.hello.o.d -nostdinc -isystem /usr/lib/gcc/i486-linux-gnu/4.4.3/include -Iinclude -I/usr/src/linux-headers-2.6.32-27-generic/arch/x86/include -include include/linux/autoconf.h -Iubuntu/include -D__KERNEL__ -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Werror-implicit-function-declaration -Wno-format-security -fno-delete-null-pointer-checks -O2 -m32 -msoft-float -mregparm=3 -freg-struct-return -mpreferred-stack-boundary=2 -march=i586 -mtune=generic -maccumulate-outgoing-args -Wa,-mtune=generic32 -ffreestanding -fstack-protector -DCONFIG_AS_CFI=1 -DCONFIG_AS_CFI_SIGNAL_FRAME=1 -pipe -Wno-sign-compare -fno-asynchronous-unwind-tables -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -Wframe-larger-than=1024 -fno-omit-frame-pointer -fno-optimize-sibling-calls -pg -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fno-dwarf2-cfi-asm -fconserve-stack -DMODULE -D"KBUILD_STR(s)=#s" -D"KBUILD_BASENAME=KBUILD_STR(hello)" -D"KBUILD_MODNAME=KBUILD_STR(hello)" -c -o /home/waffleman/tmp/mod-test/.tmp_hello.o /home/waffleman/tmp/mod-test/hello.c
set -e ; perl /usr/src/linux-headers-2.6.32-27-generic/scripts/recordmcount.pl "i386" "32" "objdump" "objcopy" "gcc" "ld" "nm" "" "" "1" "/home/waffleman/tmp/mod-test/hello.o";
(cat /dev/null; echo kernel//home/waffleman/tmp/mod-test/hello.ko;) > /home/waffleman/tmp/mod-test/modules.order
make -f /usr/src/linux-headers-2.6.32-27-generic/scripts/Makefile.modpost
scripts/mod/modpost -m -a -i /usr/src/linux-headers-2.6.32-27-generic/Module.symvers -I /home/waffleman/tmp/mod-test/Module.symvers -o /home/waffleman/tmp/mod-test/Module.symvers -S -w -s
make[1]: Leaving directory `/usr/src/linux-headers-2.6.32-27-generic'
waffleman#waffleman-desktop:~/tmp/mod-test$ cat /home/waffleman/tmp/mod-test/modules.order
kernel//home/waffleman/tmp/mod-test/hello.ko
I spent all day glued to my computer fighting this precise problem..which ended up mysteriously disappearing like for OP.
I can at least offer this meager detail from my experience: I was getting the same output as OP (for make V=1) and putting print statements in ${kernel_directory}/scripts/makefile.build showed that obj-m was strangely NOT being set after including my makefile, even though it was clearly typed as above.
I did a bunch of fooling around with the line "obj-m += hello.o" and the ones around it. Eventually it magically worked..although it looked exactly the same as before in the end. Maybe I had copied those lines from a tutorial online and it contained some sort of invalid/incorrect character?
For anyone experiencing this, verify that obj-m is in fact getting set to hello.o
If it mysteriously isn't, delete the line, hell the whole Makefile, and retype it.
I know that's not much help; I wish I could reproduce what happened!
In another thread I found that when I copy pasted the makefile contents, the -C after make was using the wrong "-" symbol and I had to re type it. It just so happens that this is the case for the obj-m += ... line above. You need to retype that character to make it valid. This should hopefully be found by anyone following the hello world module tutorial.
I guess you copied the contents of the Makefile from a PDF or some HTML document. The hyphens used are somewhat weird. Just try replacing the hyphens in the makefile; it will work like a charm.
I just ran into this same problem and for me it was caused by changing the default grep options via the GREP_OPTIONS environment variable. I didn't dig into the details, but something in the module build process didn't like my alternate grep output (include file name and line number). Removing the GREP_OPTIONS environment variable fixed things right up.
This happens because when you copy the make file contents from the PDF or any other tutorial websites and use it as it is. While you do a copy-paste, the contents will appear a bit weird in Linux environment. ie; Some special character issues will be there. If you retype the contents in Linux environment and do a make, this should work.
On the machine that fails does your .config have module support disabled?
Try doing "make menuconfig" and make sure module support is enabled.
I can only guess your kernel build environment is botched, because it passes both the theoretical check (the look of the developer) as well as the practical test:
make -C /lib/modules/2.6.36-rc8-32-desktop/build M=/dev/shm modules
make[1]: Entering directory `/usr/src/linux-2.6.36-rc8-32-obj/x86_64/desktop'
make -C ../../../linux-2.6.36-rc8-32 O=/usr/src/linux-2.6.36-rc8-32-obj/x86_64/desktop/. modules
CC [M] /dev/shm/hello.o
Building modules, stage 2.
MODPOST 1 modules
CC /dev/shm/hello.mod.o
LD [M] /dev/shm/hello.ko
make[1]: Leaving directory `/usr/src/linux-2.6.36-rc8-32-obj/x86_64/desktop'
The error mysteriously went away. If anyone has an idea what could cause this. I'd like to know in case there is a next time.
Try to remove modules string from the Makefile:
obj-m = hello.o
KVERSION = $(shell uname -r)
all:
make -C /lib/modules/$(KVERSION)/build M=$(shell pwd) # <--
clean:
make -C /lib/modules/$(KVERSION)/build M=$(shell pwd) clean
I was able to solve this problem by putting the
obj-m += <module name>.o
In a separate file named Kbuild. See Linux/documentation/kbuild/modules.txt for a hint as to why this might work
I had the same problem. Finally, I rebuilt the kernel, rewrote the makefile. It worked finally.
I guess the main reason is because I had M=$(PWD) modules in the following line right after make ARCH=arm...
I solved this problem by correcting Makefile, i.e.:
obj-m := modulename.o
I think it's not about special characters. I couldn't solve even when I manually typed! Then I tried again using kate text editor because previously I used nano and this time it worked like charm by even simple copy and paste. Because of that, I think the issue is the text editor

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