Turn 2 bit module (Multiplier) into more bits - verilog

Question

I have the following code for a 2 bit multiplier:
module Multiplier (a0, a1, b0, b1, c[3:0]);
output [3:0]c;
input a0, a1, b0, b1;
wire a0b1, a1b0, ha0c, a1b1;
and (c[0], a0, b0);
and (a0b1, a0, b1);
and (a1b0, a1, b0);
HalfAdder ha0 (a1b0, a0b1, c[1], ha0c);
and (a1b1, a1, b1);
HalfAdder ha1 (ha0c, a1b1, c[2], c[3]);
endmodule
I want to be able to expand this to more than 2 bits though (32 bits). The structure of my code poses a challenge for this though. First off I would have to have 68 parameters for the module. Also I would have to manually create 64 wires (duplicates of wire a0b1, a1b0, ha0c, a1b1). Finally I would need to manually write out a bunch of logic gates and HalfAdder modules to connect all the logic. Because of this I am wondering if there is a way that I can refactor my code to be able to instantiate a binary multiplier of n (a passed parameter) size.

Answer 1

You need to parameterize and use a generate block. (And it is much better to use a synchronous circuit then an asynchronous circuit).
Here is an incomplete example, you can fill in the necessary logic :
module Multiplier (a, b, c, clk);
parameter WIDTH = 64;
output [2*WIDTH:0]c;
input [WIDTH-1:0]a;
input [WIDTH-1:0]b;
input clk;
genvar i;
generate for (i = 0; i < WIDTH; i <= i + 1)
begin : shifts
// shift a 1-bit for each i and 'logical and' it with b
reg [WIDTH + i :0]carry;
wire [WIDTH + i -1:0]shifted = {a,i{0}} & b[i];
// sum the result of shift and 'logical and'
always # (posedge clk)
begin
carry <= shifted + shifts[i-1].carry ;
end
end
assign c = shifts[WIDTH].carry;
endgenerate
endmodule