how to solve counter for seg controller fault - verilog

Question

module seg_controller(
clk,
reset,
sel,
seg,);
input clk;
input reset;
output wire [5:0] sel;
output wire [7:0] seg;
wire [9:0] count;
wire [3:0] d_in;
counter use_counter(clk, reset, count);
FSM(count, reset, sel, d_in);
dec_7seg(d_in,seg);
endmodule
At this part, I don't know how to connect modules each others.
Each modules have many variables, but except input clk, reset how should i use variables in count, d_in.
just use wire?
module counter
(clk,
reset,
count);
input clk;
input reset;
output reg [9:0] count;
always # (posedge clk)
begin
if(reset) count <= 0;
else count <= count + 1;
end
endmodule
module FSM (
count,
reset,
sel,
d_in);
input [9:0]count;
input reset;
output reg [5:0] sel;
output reg [3:0] d_in;
reg [5:0] state, nextstate;
parameter S0 = 6'b100_000;
parameter S1 = 6'b010_000;
parameter S2 = 6'b001_000;
parameter S3 = 6'b000_100;
parameter S4 = 6'b000_010;
parameter S5 = 6'b000_001;
always # (*)
begin
if(reset) sel = 6'b100_000;
else if(count == 10'b11_1111_1111)
state = nextstate;
d_in = d_in + 1;
end
always # (*)
case(state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S3;
S3: nextstate = S4;
S4: nextstate = S5;
S5: nextstate = S0;
default: nextstate = S0;
endcase
always # (*)
if(state == S0) begin
sel = S0; end
else if(state == S1) begin
sel = S1; end
else if(state == S2) begin
sel = S2; end
else if(state == S3) begin
sel = S3; end
else if(state == S4) begin
sel = S4; end
else begin
sel = S5; end
endmodule
At this part
if(state == S0) begin
sel = S0; end
Error (10028): Can't resolve multiple constant drivers for net "sel[4]" at FSM.v(44)
I don't know why this massage come out.
module dec_7seg(
d_in,
seg
);
input [3:0]d_in;
output [7:0]seg;
wire [3:0]d;
assign d[3] = ~ d_in[3];
assign d[2] = ~ d_in[2];
assign d[1] = ~ d_in[1];
assign d[0] = ~ d_in[0];
assign seg[0] = ~(d[3] & d[2] | d[3] & d[1]);
assign seg[1] = ~(~d[2] & d[1] | d[2] & ~d[1] | d[3] & d[0] | d[1] & ~d[0]);
assign seg[2] = ~(d[3] & ~d[2] | d[3] & d[1] | ~d[3] & d[2] & ~d[1] | d[2] &
d[1] & ~d[0] | ~d[2] & ~d[1] & ~d[0]);
assign seg[3] = ~(d[3] & d[2] | d[3] & d[1] | ~d[2] & ~d[0] | d[1] & ~d[0]);
assign seg[4] = ~(d[2] & ~d[1] & d[0] | d[3] & ~d[1] | ~d[2] & d[1] & d[0] |
~d[3] & ~d[2] & ~d[0] | d[2] & d[1] & ~d[0]);
assign seg[5] = ~(~d[3] & d[2] | d[3] & ~d[2] | ~d[1] & d[0] | ~d[2] & ~d[1]
| ~d[2] & d[0]);
assign seg[6] = ~(~d[3] & d[1] & d[0] | d[3] & ~d[1] & d[0] | d[3] & d[1] &
~d[0] | ~d[3] & ~d[1]& ~d[0] | ~d[2] & ~d[1] | ~d[2] & ~d[0]);
assign seg[7] = ~(~d[3] & d[1] | d[2] & d[1] | ~d[2] & ~d[0] | d[3] & ~d[2]
& ~d[1] | ~d[3] & d[2] & d[0]);
endmodule
I want to make it work. But i'm a beginner at verilog.
There are too many problem what i don't know why.
So I want to know the direction to solve that terrible codes...

Answer 1

Your problem is that you are assigned sel here
always # (*)
begin
if(reset) sel = 6'b100_000; // <-- You should assign
// state and d_in here only
else if(count == 10'b11_1111_1111)
state = nextstate;
d_in = d_in + 1;
end
And then assigning sel in another process
always # (*)
if(state == S0) begin
sel = S0; end
else if(state == S1) begin
sel = S1; end
else if(state == S2) begin
sel = S2; end
else if(state == S3) begin
sel = S3; end
else if(state == S4) begin
sel = S4; end
else begin
sel = S5; end
endmodule
I think you want it come up in S0 on reset, so you might try this
always # (*)
if(state == S0 || reset) begin // Now you reset sel and assign in
sel = S0; end // the same process
else if(state == S1) begin
sel = S1; end
else if(state == S2) begin
sel = S2; end
else if(state == S3) begin
sel = S3; end
else if(state == S4) begin
sel = S4; end
else begin
sel = S5; end